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Diffstat (limited to 'lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/tal.h')
| -rw-r--r-- | lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/tal.h | 1842 |
1 files changed, 1842 insertions, 0 deletions
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/tal.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/tal.h new file mode 100644 index 0000000000..dc904e5569 --- /dev/null +++ b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/tal.h @@ -0,0 +1,1842 @@ +/** + * \file + * + * \brief Component description for TAL + * + * Copyright (c) 2017 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD51_TAL_COMPONENT_ +#define _SAMD51_TAL_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR TAL */ +/* ========================================================================== */ +/** \addtogroup SAMD51_TAL Trigger Allocator */ +/*@{*/ + +#define TAL_U2253 +#define REV_TAL 0x200 + +/* -------- TAL_CTRLA : (TAL Offset: 0x000) (R/W 8) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} TAL_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TAL_CTRLA_OFFSET 0x000 /**< \brief (TAL_CTRLA offset) Control A */ +#define TAL_CTRLA_RESETVALUE _U_(0x00) /**< \brief (TAL_CTRLA reset_value) Control A */ + +#define TAL_CTRLA_SWRST_Pos 0 /**< \brief (TAL_CTRLA) Software Reset */ +#define TAL_CTRLA_SWRST (_U_(0x1) << TAL_CTRLA_SWRST_Pos) +#define TAL_CTRLA_ENABLE_Pos 1 /**< \brief (TAL_CTRLA) Enable */ +#define TAL_CTRLA_ENABLE (_U_(0x1) << TAL_CTRLA_ENABLE_Pos) +#define TAL_CTRLA_MASK _U_(0x03) /**< \brief (TAL_CTRLA) MASK Register */ + +/* -------- TAL_EXTCTRL : (TAL Offset: 0x001) (R/W 8) External Break Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t ENABLE:1; /*!< bit: 0 Enable BRK Pin */ + uint8_t INV:1; /*!< bit: 1 Invert BRK Pin */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} TAL_EXTCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TAL_EXTCTRL_OFFSET 0x001 /**< \brief (TAL_EXTCTRL offset) External Break Control */ +#define TAL_EXTCTRL_RESETVALUE _U_(0x00) /**< \brief (TAL_EXTCTRL reset_value) External Break Control */ + +#define TAL_EXTCTRL_ENABLE_Pos 0 /**< \brief (TAL_EXTCTRL) Enable BRK Pin */ +#define TAL_EXTCTRL_ENABLE (_U_(0x1) << TAL_EXTCTRL_ENABLE_Pos) +#define TAL_EXTCTRL_INV_Pos 1 /**< \brief (TAL_EXTCTRL) Invert BRK Pin */ +#define TAL_EXTCTRL_INV (_U_(0x1) << TAL_EXTCTRL_INV_Pos) +#define TAL_EXTCTRL_MASK _U_(0x03) /**< \brief (TAL_EXTCTRL) MASK Register */ + +/* -------- TAL_EVCTRL : (TAL Offset: 0x004) (R/W 16) Event Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t BRKEI:1; /*!< bit: 0 Break Input Event Enable */ + uint16_t BRKEO:1; /*!< bit: 1 Break Output Event Enable */ + uint16_t IRQMONEO0:1; /*!< bit: 2 Interrupt Request Monitor 0 Output Event Enable */ + uint16_t :13; /*!< bit: 3..15 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t :2; /*!< bit: 0.. 1 Reserved */ + uint16_t IRQMONEO:1; /*!< bit: 2 Interrupt Request Monitor x Output Event Enable */ + uint16_t :13; /*!< bit: 3..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ +} TAL_EVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TAL_EVCTRL_OFFSET 0x004 /**< \brief (TAL_EVCTRL offset) Event Control */ +#define TAL_EVCTRL_RESETVALUE _U_(0x0000) /**< \brief (TAL_EVCTRL reset_value) Event Control */ + +#define TAL_EVCTRL_BRKEI_Pos 0 /**< \brief (TAL_EVCTRL) Break Input Event Enable */ +#define TAL_EVCTRL_BRKEI (_U_(0x1) << TAL_EVCTRL_BRKEI_Pos) +#define TAL_EVCTRL_BRKEO_Pos 1 /**< \brief (TAL_EVCTRL) Break Output Event Enable */ +#define TAL_EVCTRL_BRKEO (_U_(0x1) << TAL_EVCTRL_BRKEO_Pos) +#define TAL_EVCTRL_IRQMONEO0_Pos 2 /**< \brief (TAL_EVCTRL) Interrupt Request Monitor 0 Output Event Enable */ +#define TAL_EVCTRL_IRQMONEO0 (_U_(1) << TAL_EVCTRL_IRQMONEO0_Pos) +#define TAL_EVCTRL_IRQMONEO_Pos 2 /**< \brief (TAL_EVCTRL) Interrupt Request Monitor x Output Event Enable */ +#define TAL_EVCTRL_IRQMONEO_Msk (_U_(0x1) << TAL_EVCTRL_IRQMONEO_Pos) +#define TAL_EVCTRL_IRQMONEO(value) (TAL_EVCTRL_IRQMONEO_Msk & ((value) << TAL_EVCTRL_IRQMONEO_Pos)) +#define TAL_EVCTRL_MASK _U_(0x0007) /**< \brief (TAL_EVCTRL) MASK Register */ + +/* -------- TAL_INTENCLR : (TAL Offset: 0x008) (R/W 8) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t BRK:1; /*!< bit: 0 Break Interrupt Enable */ + uint8_t IPS0:1; /*!< bit: 1 Inter-Processor Signal Interrupt Enable for CPU 0 */ + uint8_t IPS1:1; /*!< bit: 2 Inter-Processor Signal Interrupt Enable for CPU 1 */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t :1; /*!< bit: 0 Reserved */ + uint8_t IPS:2; /*!< bit: 1.. 2 Inter-Processor Signal Interrupt Enable for CPU x */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} TAL_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TAL_INTENCLR_OFFSET 0x008 /**< \brief (TAL_INTENCLR offset) Interrupt Enable Clear */ +#define TAL_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (TAL_INTENCLR reset_value) Interrupt Enable Clear */ + +#define TAL_INTENCLR_BRK_Pos 0 /**< \brief (TAL_INTENCLR) Break Interrupt Enable */ +#define TAL_INTENCLR_BRK (_U_(0x1) << TAL_INTENCLR_BRK_Pos) +#define TAL_INTENCLR_IPS0_Pos 1 /**< \brief (TAL_INTENCLR) Inter-Processor Signal Interrupt Enable for CPU 0 */ +#define TAL_INTENCLR_IPS0 (_U_(1) << TAL_INTENCLR_IPS0_Pos) +#define TAL_INTENCLR_IPS1_Pos 2 /**< \brief (TAL_INTENCLR) Inter-Processor Signal Interrupt Enable for CPU 1 */ +#define TAL_INTENCLR_IPS1 (_U_(1) << TAL_INTENCLR_IPS1_Pos) +#define TAL_INTENCLR_IPS_Pos 1 /**< \brief (TAL_INTENCLR) Inter-Processor Signal Interrupt Enable for CPU x */ +#define TAL_INTENCLR_IPS_Msk (_U_(0x3) << TAL_INTENCLR_IPS_Pos) +#define TAL_INTENCLR_IPS(value) (TAL_INTENCLR_IPS_Msk & ((value) << TAL_INTENCLR_IPS_Pos)) +#define TAL_INTENCLR_MASK _U_(0x07) /**< \brief (TAL_INTENCLR) MASK Register */ + +/* -------- TAL_INTENSET : (TAL Offset: 0x009) (R/W 8) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t BRK:1; /*!< bit: 0 Break Interrupt Enable */ + uint8_t IPS0:1; /*!< bit: 1 Inter-Processor Signal Interrupt Enable for CPU 0 */ + uint8_t IPS1:1; /*!< bit: 2 Inter-Processor Signal Interrupt Enable for CPU 1 */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t :1; /*!< bit: 0 Reserved */ + uint8_t IPS:2; /*!< bit: 1.. 2 Inter-Processor Signal Interrupt Enable for CPU x */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} TAL_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TAL_INTENSET_OFFSET 0x009 /**< \brief (TAL_INTENSET offset) Interrupt Enable Set */ +#define TAL_INTENSET_RESETVALUE _U_(0x00) /**< \brief (TAL_INTENSET reset_value) Interrupt Enable Set */ + +#define TAL_INTENSET_BRK_Pos 0 /**< \brief (TAL_INTENSET) Break Interrupt Enable */ +#define TAL_INTENSET_BRK (_U_(0x1) << TAL_INTENSET_BRK_Pos) +#define TAL_INTENSET_IPS0_Pos 1 /**< \brief (TAL_INTENSET) Inter-Processor Signal Interrupt Enable for CPU 0 */ +#define TAL_INTENSET_IPS0 (_U_(1) << TAL_INTENSET_IPS0_Pos) +#define TAL_INTENSET_IPS1_Pos 2 /**< \brief (TAL_INTENSET) Inter-Processor Signal Interrupt Enable for CPU 1 */ +#define TAL_INTENSET_IPS1 (_U_(1) << TAL_INTENSET_IPS1_Pos) +#define TAL_INTENSET_IPS_Pos 1 /**< \brief (TAL_INTENSET) Inter-Processor Signal Interrupt Enable for CPU x */ +#define TAL_INTENSET_IPS_Msk (_U_(0x3) << TAL_INTENSET_IPS_Pos) +#define TAL_INTENSET_IPS(value) (TAL_INTENSET_IPS_Msk & ((value) << TAL_INTENSET_IPS_Pos)) +#define TAL_INTENSET_MASK _U_(0x07) /**< \brief (TAL_INTENSET) MASK Register */ + +/* -------- TAL_INTFLAG : (TAL Offset: 0x00A) (R/W 8) Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t BRK:1; /*!< bit: 0 Break */ + __I uint8_t IPS0:1; /*!< bit: 1 Inter-Processor Signal for CPU 0 */ + __I uint8_t IPS1:1; /*!< bit: 2 Inter-Processor Signal for CPU 1 */ + __I uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + __I uint8_t :1; /*!< bit: 0 Reserved */ + __I uint8_t IPS:2; /*!< bit: 1.. 2 Inter-Processor Signal for CPU x */ + __I uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} TAL_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TAL_INTFLAG_OFFSET 0x00A /**< \brief (TAL_INTFLAG offset) Interrupt Flag Status and Clear */ +#define TAL_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (TAL_INTFLAG reset_value) Interrupt Flag Status and Clear */ + +#define TAL_INTFLAG_BRK_Pos 0 /**< \brief (TAL_INTFLAG) Break */ +#define TAL_INTFLAG_BRK (_U_(0x1) << TAL_INTFLAG_BRK_Pos) +#define TAL_INTFLAG_IPS0_Pos 1 /**< \brief (TAL_INTFLAG) Inter-Processor Signal for CPU 0 */ +#define TAL_INTFLAG_IPS0 (_U_(1) << TAL_INTFLAG_IPS0_Pos) +#define TAL_INTFLAG_IPS1_Pos 2 /**< \brief (TAL_INTFLAG) Inter-Processor Signal for CPU 1 */ +#define TAL_INTFLAG_IPS1 (_U_(1) << TAL_INTFLAG_IPS1_Pos) +#define TAL_INTFLAG_IPS_Pos 1 /**< \brief (TAL_INTFLAG) Inter-Processor Signal for CPU x */ +#define TAL_INTFLAG_IPS_Msk (_U_(0x3) << TAL_INTFLAG_IPS_Pos) +#define TAL_INTFLAG_IPS(value) (TAL_INTFLAG_IPS_Msk & ((value) << TAL_INTFLAG_IPS_Pos)) +#define TAL_INTFLAG_MASK _U_(0x07) /**< \brief (TAL_INTFLAG) MASK Register */ + +/* -------- TAL_GLOBMASK : (TAL Offset: 0x00B) (R/W 8) Global Break Requests Mask -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t CPU0:1; /*!< bit: 0 CPU 0 Break Master */ + uint8_t CPU1:1; /*!< bit: 1 CPU 1 Break Master */ + uint8_t :4; /*!< bit: 2.. 5 Reserved */ + uint8_t EVBRK:1; /*!< bit: 6 Event Break Master */ + uint8_t EXTBRK:1; /*!< bit: 7 External Break Master */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t CPU:2; /*!< bit: 0.. 1 CPU x Break Master */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} TAL_GLOBMASK_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TAL_GLOBMASK_OFFSET 0x00B /**< \brief (TAL_GLOBMASK offset) Global Break Requests Mask */ +#define TAL_GLOBMASK_RESETVALUE _U_(0x00) /**< \brief (TAL_GLOBMASK reset_value) Global Break Requests Mask */ + +#define TAL_GLOBMASK_CPU0_Pos 0 /**< \brief (TAL_GLOBMASK) CPU 0 Break Master */ +#define TAL_GLOBMASK_CPU0 (_U_(1) << TAL_GLOBMASK_CPU0_Pos) +#define TAL_GLOBMASK_CPU1_Pos 1 /**< \brief (TAL_GLOBMASK) CPU 1 Break Master */ +#define TAL_GLOBMASK_CPU1 (_U_(1) << TAL_GLOBMASK_CPU1_Pos) +#define TAL_GLOBMASK_CPU_Pos 0 /**< \brief (TAL_GLOBMASK) CPU x Break Master */ +#define TAL_GLOBMASK_CPU_Msk (_U_(0x3) << TAL_GLOBMASK_CPU_Pos) +#define TAL_GLOBMASK_CPU(value) (TAL_GLOBMASK_CPU_Msk & ((value) << TAL_GLOBMASK_CPU_Pos)) +#define TAL_GLOBMASK_EVBRK_Pos 6 /**< \brief (TAL_GLOBMASK) Event Break Master */ +#define TAL_GLOBMASK_EVBRK (_U_(0x1) << TAL_GLOBMASK_EVBRK_Pos) +#define TAL_GLOBMASK_EXTBRK_Pos 7 /**< \brief (TAL_GLOBMASK) External Break Master */ +#define TAL_GLOBMASK_EXTBRK (_U_(0x1) << TAL_GLOBMASK_EXTBRK_Pos) +#define TAL_GLOBMASK_MASK _U_(0xC3) /**< \brief (TAL_GLOBMASK) MASK Register */ + +/* -------- TAL_HALT : (TAL Offset: 0x00C) ( /W 8) Debug Halt Request -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t CPU0:1; /*!< bit: 0 CPU 0 Break Master */ + uint8_t CPU1:1; /*!< bit: 1 CPU 1 Break Master */ + uint8_t :4; /*!< bit: 2.. 5 Reserved */ + uint8_t EVBRK:1; /*!< bit: 6 Event Break Master */ + uint8_t EXTBRK:1; /*!< bit: 7 External Break Master */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t CPU:2; /*!< bit: 0.. 1 CPU x Break Master */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} TAL_HALT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TAL_HALT_OFFSET 0x00C /**< \brief (TAL_HALT offset) Debug Halt Request */ +#define TAL_HALT_RESETVALUE _U_(0x00) /**< \brief (TAL_HALT reset_value) Debug Halt Request */ + +#define TAL_HALT_CPU0_Pos 0 /**< \brief (TAL_HALT) CPU 0 Break Master */ +#define TAL_HALT_CPU0 (_U_(1) << TAL_HALT_CPU0_Pos) +#define TAL_HALT_CPU1_Pos 1 /**< \brief (TAL_HALT) CPU 1 Break Master */ +#define TAL_HALT_CPU1 (_U_(1) << TAL_HALT_CPU1_Pos) +#define TAL_HALT_CPU_Pos 0 /**< \brief (TAL_HALT) CPU x Break Master */ +#define TAL_HALT_CPU_Msk (_U_(0x3) << TAL_HALT_CPU_Pos) +#define TAL_HALT_CPU(value) (TAL_HALT_CPU_Msk & ((value) << TAL_HALT_CPU_Pos)) +#define TAL_HALT_EVBRK_Pos 6 /**< \brief (TAL_HALT) Event Break Master */ +#define TAL_HALT_EVBRK (_U_(0x1) << TAL_HALT_EVBRK_Pos) +#define TAL_HALT_EXTBRK_Pos 7 /**< \brief (TAL_HALT) External Break Master */ +#define TAL_HALT_EXTBRK (_U_(0x1) << TAL_HALT_EXTBRK_Pos) +#define TAL_HALT_MASK _U_(0xC3) /**< \brief (TAL_HALT) MASK Register */ + +/* -------- TAL_RESTART : (TAL Offset: 0x00D) ( /W 8) Debug Restart Request -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t CPU0:1; /*!< bit: 0 CPU 0 Break Master */ + uint8_t CPU1:1; /*!< bit: 1 CPU 1 Break Master */ + uint8_t :5; /*!< bit: 2.. 6 Reserved */ + uint8_t EXTBRK:1; /*!< bit: 7 External Break Master */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t CPU:2; /*!< bit: 0.. 1 CPU x Break Master */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} TAL_RESTART_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TAL_RESTART_OFFSET 0x00D /**< \brief (TAL_RESTART offset) Debug Restart Request */ +#define TAL_RESTART_RESETVALUE _U_(0x00) /**< \brief (TAL_RESTART reset_value) Debug Restart Request */ + +#define TAL_RESTART_CPU0_Pos 0 /**< \brief (TAL_RESTART) CPU 0 Break Master */ +#define TAL_RESTART_CPU0 (_U_(1) << TAL_RESTART_CPU0_Pos) +#define TAL_RESTART_CPU1_Pos 1 /**< \brief (TAL_RESTART) CPU 1 Break Master */ +#define TAL_RESTART_CPU1 (_U_(1) << TAL_RESTART_CPU1_Pos) +#define TAL_RESTART_CPU_Pos 0 /**< \brief (TAL_RESTART) CPU x Break Master */ +#define TAL_RESTART_CPU_Msk (_U_(0x3) << TAL_RESTART_CPU_Pos) +#define TAL_RESTART_CPU(value) (TAL_RESTART_CPU_Msk & ((value) << TAL_RESTART_CPU_Pos)) +#define TAL_RESTART_EXTBRK_Pos 7 /**< \brief (TAL_RESTART) External Break Master */ +#define TAL_RESTART_EXTBRK (_U_(0x1) << TAL_RESTART_EXTBRK_Pos) +#define TAL_RESTART_MASK _U_(0x83) /**< \brief (TAL_RESTART) MASK Register */ + +/* -------- TAL_BRKSTATUS : (TAL Offset: 0x00E) (R/ 16) Break Request Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t CPU0:2; /*!< bit: 0.. 1 CPU 0 Break Request */ + uint16_t CPU1:2; /*!< bit: 2.. 3 CPU 1 Break Request */ + uint16_t :8; /*!< bit: 4..11 Reserved */ + uint16_t EVBRK:2; /*!< bit: 12..13 Event Break Request */ + uint16_t EXTBRK:2; /*!< bit: 14..15 External Break Request */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} TAL_BRKSTATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TAL_BRKSTATUS_OFFSET 0x00E /**< \brief (TAL_BRKSTATUS offset) Break Request Status */ +#define TAL_BRKSTATUS_RESETVALUE _U_(0x0000) /**< \brief (TAL_BRKSTATUS reset_value) Break Request Status */ + +#define TAL_BRKSTATUS_CPU0_Pos 0 /**< \brief (TAL_BRKSTATUS) CPU 0 Break Request */ +#define TAL_BRKSTATUS_CPU0_Msk (_U_(0x3) << TAL_BRKSTATUS_CPU0_Pos) +#define TAL_BRKSTATUS_CPU0(value) (TAL_BRKSTATUS_CPU0_Msk & ((value) << TAL_BRKSTATUS_CPU0_Pos)) +#define TAL_BRKSTATUS_CPU1_Pos 2 /**< \brief (TAL_BRKSTATUS) CPU 1 Break Request */ +#define TAL_BRKSTATUS_CPU1_Msk (_U_(0x3) << TAL_BRKSTATUS_CPU1_Pos) +#define TAL_BRKSTATUS_CPU1(value) (TAL_BRKSTATUS_CPU1_Msk & ((value) << TAL_BRKSTATUS_CPU1_Pos)) +#define TAL_BRKSTATUS_EVBRK_Pos 12 /**< \brief (TAL_BRKSTATUS) Event Break Request */ +#define TAL_BRKSTATUS_EVBRK_Msk (_U_(0x3) << TAL_BRKSTATUS_EVBRK_Pos) +#define TAL_BRKSTATUS_EVBRK(value) (TAL_BRKSTATUS_EVBRK_Msk & ((value) << TAL_BRKSTATUS_EVBRK_Pos)) +#define TAL_BRKSTATUS_EXTBRK_Pos 14 /**< \brief (TAL_BRKSTATUS) External Break Request */ +#define TAL_BRKSTATUS_EXTBRK_Msk (_U_(0x3) << TAL_BRKSTATUS_EXTBRK_Pos) +#define TAL_BRKSTATUS_EXTBRK(value) (TAL_BRKSTATUS_EXTBRK_Msk & ((value) << TAL_BRKSTATUS_EXTBRK_Pos)) +#define TAL_BRKSTATUS_MASK _U_(0xF00F) /**< \brief (TAL_BRKSTATUS) MASK Register */ + +/* -------- TAL_CTICTRLA : (TAL Offset: 0x010) (R/W 8) CTIS Cross-Trigger Interface n Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t BRK:2; /*!< bit: 0.. 1 Action when global break issued */ + uint8_t RESTART:1; /*!< bit: 2 Action when global restart issued */ + uint8_t IPS:1; /*!< bit: 3 Action when inter-process resource freed */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} TAL_CTICTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TAL_CTICTRLA_OFFSET 0x010 /**< \brief (TAL_CTICTRLA offset) Cross-Trigger Interface n Control A */ +#define TAL_CTICTRLA_RESETVALUE _U_(0x00) /**< \brief (TAL_CTICTRLA reset_value) Cross-Trigger Interface n Control A */ + +#define TAL_CTICTRLA_BRK_Pos 0 /**< \brief (TAL_CTICTRLA) Action when global break issued */ +#define TAL_CTICTRLA_BRK_Msk (_U_(0x3) << TAL_CTICTRLA_BRK_Pos) +#define TAL_CTICTRLA_BRK(value) (TAL_CTICTRLA_BRK_Msk & ((value) << TAL_CTICTRLA_BRK_Pos)) +#define TAL_CTICTRLA_BRK_BREAK_Val _U_(0x0) /**< \brief (TAL_CTICTRLA) Break when requested */ +#define TAL_CTICTRLA_BRK_INTERRUPT_Val _U_(0x1) /**< \brief (TAL_CTICTRLA) Trigger DBG interrupt instead of break */ +#define TAL_CTICTRLA_BRK_IGNORE_Val _U_(0x2) /**< \brief (TAL_CTICTRLA) Ignore break request */ +#define TAL_CTICTRLA_BRK_BREAK (TAL_CTICTRLA_BRK_BREAK_Val << TAL_CTICTRLA_BRK_Pos) +#define TAL_CTICTRLA_BRK_INTERRUPT (TAL_CTICTRLA_BRK_INTERRUPT_Val << TAL_CTICTRLA_BRK_Pos) +#define TAL_CTICTRLA_BRK_IGNORE (TAL_CTICTRLA_BRK_IGNORE_Val << TAL_CTICTRLA_BRK_Pos) +#define TAL_CTICTRLA_RESTART_Pos 2 /**< \brief (TAL_CTICTRLA) Action when global restart issued */ +#define TAL_CTICTRLA_RESTART (_U_(0x1) << TAL_CTICTRLA_RESTART_Pos) +#define TAL_CTICTRLA_RESTART_RESTART_Val _U_(0x0) /**< \brief (TAL_CTICTRLA) Restart when requested */ +#define TAL_CTICTRLA_RESTART_IGNORE_Val _U_(0x1) /**< \brief (TAL_CTICTRLA) Ignore restart request */ +#define TAL_CTICTRLA_RESTART_RESTART (TAL_CTICTRLA_RESTART_RESTART_Val << TAL_CTICTRLA_RESTART_Pos) +#define TAL_CTICTRLA_RESTART_IGNORE (TAL_CTICTRLA_RESTART_IGNORE_Val << TAL_CTICTRLA_RESTART_Pos) +#define TAL_CTICTRLA_IPS_Pos 3 /**< \brief (TAL_CTICTRLA) Action when inter-process resource freed */ +#define TAL_CTICTRLA_IPS (_U_(0x1) << TAL_CTICTRLA_IPS_Pos) +#define TAL_CTICTRLA_IPS_EVENT_Val _U_(0x0) /**< \brief (TAL_CTICTRLA) Generate CPU Event when awaited resource is freed. */ +#define TAL_CTICTRLA_IPS_INTERRUPT_Val _U_(0x1) /**< \brief (TAL_CTICTRLA) Generate Interrupt when awaited resource is freed. */ +#define TAL_CTICTRLA_IPS_EVENT (TAL_CTICTRLA_IPS_EVENT_Val << TAL_CTICTRLA_IPS_Pos) +#define TAL_CTICTRLA_IPS_INTERRUPT (TAL_CTICTRLA_IPS_INTERRUPT_Val << TAL_CTICTRLA_IPS_Pos) +#define TAL_CTICTRLA_MASK _U_(0x0F) /**< \brief (TAL_CTICTRLA) MASK Register */ + +/* -------- TAL_CTIMASK : (TAL Offset: 0x011) (R/W 8) CTIS Cross-Trigger Interface n Mask -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t CPU0:1; /*!< bit: 0 CPU 0 Break Master */ + uint8_t CPU1:1; /*!< bit: 1 CPU 1 Break Master */ + uint8_t :4; /*!< bit: 2.. 5 Reserved */ + uint8_t EVBRK:1; /*!< bit: 6 Event Break Master */ + uint8_t EXTBRK:1; /*!< bit: 7 External Break Master */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t CPU:2; /*!< bit: 0.. 1 CPU x Break Master */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} TAL_CTIMASK_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TAL_CTIMASK_OFFSET 0x011 /**< \brief (TAL_CTIMASK offset) Cross-Trigger Interface n Mask */ +#define TAL_CTIMASK_RESETVALUE _U_(0x00) /**< \brief (TAL_CTIMASK reset_value) Cross-Trigger Interface n Mask */ + +#define TAL_CTIMASK_CPU0_Pos 0 /**< \brief (TAL_CTIMASK) CPU 0 Break Master */ +#define TAL_CTIMASK_CPU0 (_U_(1) << TAL_CTIMASK_CPU0_Pos) +#define TAL_CTIMASK_CPU1_Pos 1 /**< \brief (TAL_CTIMASK) CPU 1 Break Master */ +#define TAL_CTIMASK_CPU1 (_U_(1) << TAL_CTIMASK_CPU1_Pos) +#define TAL_CTIMASK_CPU_Pos 0 /**< \brief (TAL_CTIMASK) CPU x Break Master */ +#define TAL_CTIMASK_CPU_Msk (_U_(0x3) << TAL_CTIMASK_CPU_Pos) +#define TAL_CTIMASK_CPU(value) (TAL_CTIMASK_CPU_Msk & ((value) << TAL_CTIMASK_CPU_Pos)) +#define TAL_CTIMASK_EVBRK_Pos 6 /**< \brief (TAL_CTIMASK) Event Break Master */ +#define TAL_CTIMASK_EVBRK (_U_(0x1) << TAL_CTIMASK_EVBRK_Pos) +#define TAL_CTIMASK_EXTBRK_Pos 7 /**< \brief (TAL_CTIMASK) External Break Master */ +#define TAL_CTIMASK_EXTBRK (_U_(0x1) << TAL_CTIMASK_EXTBRK_Pos) +#define TAL_CTIMASK_MASK _U_(0xC3) /**< \brief (TAL_CTIMASK) MASK Register */ + +/* -------- TAL_INTSTATUS : (TAL Offset: 0x020) (R/ 8) Interrupt n Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t IRQ0:1; /*!< bit: 0 Interrupt Status for Interrupt Request 0 within Interrupt n */ + uint8_t IRQ1:1; /*!< bit: 1 Interrupt Status for Interrupt Request 1 within Interrupt n */ + uint8_t IRQ2:1; /*!< bit: 2 Interrupt Status for Interrupt Request 2 within Interrupt n */ + uint8_t IRQ3:1; /*!< bit: 3 Interrupt Status for Interrupt Request 3 within Interrupt n */ + uint8_t IRQ4:1; /*!< bit: 4 Interrupt Status for Interrupt Request 4 within Interrupt n */ + uint8_t IRQ5:1; /*!< bit: 5 Interrupt Status for Interrupt Request 5 within Interrupt n */ + uint8_t IRQ6:1; /*!< bit: 6 Interrupt Status for Interrupt Request 6 within Interrupt n */ + uint8_t IRQ7:1; /*!< bit: 7 Interrupt Status for Interrupt Request 7 within Interrupt n */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t IRQ:8; /*!< bit: 0.. 7 Interrupt Status for Interrupt Request x within Interrupt n */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} TAL_INTSTATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TAL_INTSTATUS_OFFSET 0x020 /**< \brief (TAL_INTSTATUS offset) Interrupt n Status */ +#define TAL_INTSTATUS_RESETVALUE _U_(0x00) /**< \brief (TAL_INTSTATUS reset_value) Interrupt n Status */ + +#define TAL_INTSTATUS_IRQ0_Pos 0 /**< \brief (TAL_INTSTATUS) Interrupt Status for Interrupt Request 0 within Interrupt n */ +#define TAL_INTSTATUS_IRQ0 (_U_(1) << TAL_INTSTATUS_IRQ0_Pos) +#define TAL_INTSTATUS_IRQ1_Pos 1 /**< \brief (TAL_INTSTATUS) Interrupt Status for Interrupt Request 1 within Interrupt n */ +#define TAL_INTSTATUS_IRQ1 (_U_(1) << TAL_INTSTATUS_IRQ1_Pos) +#define TAL_INTSTATUS_IRQ2_Pos 2 /**< \brief (TAL_INTSTATUS) Interrupt Status for Interrupt Request 2 within Interrupt n */ +#define TAL_INTSTATUS_IRQ2 (_U_(1) << TAL_INTSTATUS_IRQ2_Pos) +#define TAL_INTSTATUS_IRQ3_Pos 3 /**< \brief (TAL_INTSTATUS) Interrupt Status for Interrupt Request 3 within Interrupt n */ +#define TAL_INTSTATUS_IRQ3 (_U_(1) << TAL_INTSTATUS_IRQ3_Pos) +#define TAL_INTSTATUS_IRQ4_Pos 4 /**< \brief (TAL_INTSTATUS) Interrupt Status for Interrupt Request 4 within Interrupt n */ +#define TAL_INTSTATUS_IRQ4 (_U_(1) << TAL_INTSTATUS_IRQ4_Pos) +#define TAL_INTSTATUS_IRQ5_Pos 5 /**< \brief (TAL_INTSTATUS) Interrupt Status for Interrupt Request 5 within Interrupt n */ +#define TAL_INTSTATUS_IRQ5 (_U_(1) << TAL_INTSTATUS_IRQ5_Pos) +#define TAL_INTSTATUS_IRQ6_Pos 6 /**< \brief (TAL_INTSTATUS) Interrupt Status for Interrupt Request 6 within Interrupt n */ +#define TAL_INTSTATUS_IRQ6 (_U_(1) << TAL_INTSTATUS_IRQ6_Pos) +#define TAL_INTSTATUS_IRQ7_Pos 7 /**< \brief (TAL_INTSTATUS) Interrupt Status for Interrupt Request 7 within Interrupt n */ +#define TAL_INTSTATUS_IRQ7 (_U_(1) << TAL_INTSTATUS_IRQ7_Pos) +#define TAL_INTSTATUS_IRQ_Pos 0 /**< \brief (TAL_INTSTATUS) Interrupt Status for Interrupt Request x within Interrupt n */ +#define TAL_INTSTATUS_IRQ_Msk (_U_(0xFF) << TAL_INTSTATUS_IRQ_Pos) +#define TAL_INTSTATUS_IRQ(value) (TAL_INTSTATUS_IRQ_Msk & ((value) << TAL_INTSTATUS_IRQ_Pos)) +#define TAL_INTSTATUS_MASK _U_(0xFF) /**< \brief (TAL_INTSTATUS) MASK Register */ + +/* -------- TAL_DMACPUSEL0 : (TAL Offset: 0x110) (R/W 32) DMA Channel Interrupts CPU Select 0 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CH0:1; /*!< bit: 0 DMA Channel 0 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 1 Reserved */ + uint32_t CH1:1; /*!< bit: 2 DMA Channel 1 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 3 Reserved */ + uint32_t CH2:1; /*!< bit: 4 DMA Channel 2 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 5 Reserved */ + uint32_t CH3:1; /*!< bit: 6 DMA Channel 3 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t CH4:1; /*!< bit: 8 DMA Channel 4 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 9 Reserved */ + uint32_t CH5:1; /*!< bit: 10 DMA Channel 5 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 11 Reserved */ + uint32_t CH6:1; /*!< bit: 12 DMA Channel 6 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 13 Reserved */ + uint32_t CH7:1; /*!< bit: 14 DMA Channel 7 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 15 Reserved */ + uint32_t CH8:1; /*!< bit: 16 DMA Channel 8 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 17 Reserved */ + uint32_t CH9:1; /*!< bit: 18 DMA Channel 9 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 19 Reserved */ + uint32_t CH10:1; /*!< bit: 20 DMA Channel 10 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 21 Reserved */ + uint32_t CH11:1; /*!< bit: 22 DMA Channel 11 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 23 Reserved */ + uint32_t CH12:1; /*!< bit: 24 DMA Channel 12 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 25 Reserved */ + uint32_t CH13:1; /*!< bit: 26 DMA Channel 13 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 27 Reserved */ + uint32_t CH14:1; /*!< bit: 28 DMA Channel 14 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 29 Reserved */ + uint32_t CH15:1; /*!< bit: 30 DMA Channel 15 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} TAL_DMACPUSEL0_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TAL_DMACPUSEL0_OFFSET 0x110 /**< \brief (TAL_DMACPUSEL0 offset) DMA Channel Interrupts CPU Select 0 */ +#define TAL_DMACPUSEL0_RESETVALUE _U_(0x00000000) /**< \brief (TAL_DMACPUSEL0 reset_value) DMA Channel Interrupts CPU Select 0 */ + +#define TAL_DMACPUSEL0_CH0_Pos 0 /**< \brief (TAL_DMACPUSEL0) DMA Channel 0 Interrupt CPU Select */ +#define TAL_DMACPUSEL0_CH0_Msk (_U_(0x1) << TAL_DMACPUSEL0_CH0_Pos) +#define TAL_DMACPUSEL0_CH0(value) (TAL_DMACPUSEL0_CH0_Msk & ((value) << TAL_DMACPUSEL0_CH0_Pos)) +#define TAL_DMACPUSEL0_CH1_Pos 2 /**< \brief (TAL_DMACPUSEL0) DMA Channel 1 Interrupt CPU Select */ +#define TAL_DMACPUSEL0_CH1_Msk (_U_(0x1) << TAL_DMACPUSEL0_CH1_Pos) +#define TAL_DMACPUSEL0_CH1(value) (TAL_DMACPUSEL0_CH1_Msk & ((value) << TAL_DMACPUSEL0_CH1_Pos)) +#define TAL_DMACPUSEL0_CH2_Pos 4 /**< \brief (TAL_DMACPUSEL0) DMA Channel 2 Interrupt CPU Select */ +#define TAL_DMACPUSEL0_CH2_Msk (_U_(0x1) << TAL_DMACPUSEL0_CH2_Pos) +#define TAL_DMACPUSEL0_CH2(value) (TAL_DMACPUSEL0_CH2_Msk & ((value) << TAL_DMACPUSEL0_CH2_Pos)) +#define TAL_DMACPUSEL0_CH3_Pos 6 /**< \brief (TAL_DMACPUSEL0) DMA Channel 3 Interrupt CPU Select */ +#define TAL_DMACPUSEL0_CH3_Msk (_U_(0x1) << TAL_DMACPUSEL0_CH3_Pos) +#define TAL_DMACPUSEL0_CH3(value) (TAL_DMACPUSEL0_CH3_Msk & ((value) << TAL_DMACPUSEL0_CH3_Pos)) +#define TAL_DMACPUSEL0_CH4_Pos 8 /**< \brief (TAL_DMACPUSEL0) DMA Channel 4 Interrupt CPU Select */ +#define TAL_DMACPUSEL0_CH4_Msk (_U_(0x1) << TAL_DMACPUSEL0_CH4_Pos) +#define TAL_DMACPUSEL0_CH4(value) (TAL_DMACPUSEL0_CH4_Msk & ((value) << TAL_DMACPUSEL0_CH4_Pos)) +#define TAL_DMACPUSEL0_CH5_Pos 10 /**< \brief (TAL_DMACPUSEL0) DMA Channel 5 Interrupt CPU Select */ +#define TAL_DMACPUSEL0_CH5_Msk (_U_(0x1) << TAL_DMACPUSEL0_CH5_Pos) +#define TAL_DMACPUSEL0_CH5(value) (TAL_DMACPUSEL0_CH5_Msk & ((value) << TAL_DMACPUSEL0_CH5_Pos)) +#define TAL_DMACPUSEL0_CH6_Pos 12 /**< \brief (TAL_DMACPUSEL0) DMA Channel 6 Interrupt CPU Select */ +#define TAL_DMACPUSEL0_CH6_Msk (_U_(0x1) << TAL_DMACPUSEL0_CH6_Pos) +#define TAL_DMACPUSEL0_CH6(value) (TAL_DMACPUSEL0_CH6_Msk & ((value) << TAL_DMACPUSEL0_CH6_Pos)) +#define TAL_DMACPUSEL0_CH7_Pos 14 /**< \brief (TAL_DMACPUSEL0) DMA Channel 7 Interrupt CPU Select */ +#define TAL_DMACPUSEL0_CH7_Msk (_U_(0x1) << TAL_DMACPUSEL0_CH7_Pos) +#define TAL_DMACPUSEL0_CH7(value) (TAL_DMACPUSEL0_CH7_Msk & ((value) << TAL_DMACPUSEL0_CH7_Pos)) +#define TAL_DMACPUSEL0_CH8_Pos 16 /**< \brief (TAL_DMACPUSEL0) DMA Channel 8 Interrupt CPU Select */ +#define TAL_DMACPUSEL0_CH8_Msk (_U_(0x1) << TAL_DMACPUSEL0_CH8_Pos) +#define TAL_DMACPUSEL0_CH8(value) (TAL_DMACPUSEL0_CH8_Msk & ((value) << TAL_DMACPUSEL0_CH8_Pos)) +#define TAL_DMACPUSEL0_CH9_Pos 18 /**< \brief (TAL_DMACPUSEL0) DMA Channel 9 Interrupt CPU Select */ +#define TAL_DMACPUSEL0_CH9_Msk (_U_(0x1) << TAL_DMACPUSEL0_CH9_Pos) +#define TAL_DMACPUSEL0_CH9(value) (TAL_DMACPUSEL0_CH9_Msk & ((value) << TAL_DMACPUSEL0_CH9_Pos)) +#define TAL_DMACPUSEL0_CH10_Pos 20 /**< \brief (TAL_DMACPUSEL0) DMA Channel 10 Interrupt CPU Select */ +#define TAL_DMACPUSEL0_CH10_Msk (_U_(0x1) << TAL_DMACPUSEL0_CH10_Pos) +#define TAL_DMACPUSEL0_CH10(value) (TAL_DMACPUSEL0_CH10_Msk & ((value) << TAL_DMACPUSEL0_CH10_Pos)) +#define TAL_DMACPUSEL0_CH11_Pos 22 /**< \brief (TAL_DMACPUSEL0) DMA Channel 11 Interrupt CPU Select */ +#define TAL_DMACPUSEL0_CH11_Msk (_U_(0x1) << TAL_DMACPUSEL0_CH11_Pos) +#define TAL_DMACPUSEL0_CH11(value) (TAL_DMACPUSEL0_CH11_Msk & ((value) << TAL_DMACPUSEL0_CH11_Pos)) +#define TAL_DMACPUSEL0_CH12_Pos 24 /**< \brief (TAL_DMACPUSEL0) DMA Channel 12 Interrupt CPU Select */ +#define TAL_DMACPUSEL0_CH12_Msk (_U_(0x1) << TAL_DMACPUSEL0_CH12_Pos) +#define TAL_DMACPUSEL0_CH12(value) (TAL_DMACPUSEL0_CH12_Msk & ((value) << TAL_DMACPUSEL0_CH12_Pos)) +#define TAL_DMACPUSEL0_CH13_Pos 26 /**< \brief (TAL_DMACPUSEL0) DMA Channel 13 Interrupt CPU Select */ +#define TAL_DMACPUSEL0_CH13_Msk (_U_(0x1) << TAL_DMACPUSEL0_CH13_Pos) +#define TAL_DMACPUSEL0_CH13(value) (TAL_DMACPUSEL0_CH13_Msk & ((value) << TAL_DMACPUSEL0_CH13_Pos)) +#define TAL_DMACPUSEL0_CH14_Pos 28 /**< \brief (TAL_DMACPUSEL0) DMA Channel 14 Interrupt CPU Select */ +#define TAL_DMACPUSEL0_CH14_Msk (_U_(0x1) << TAL_DMACPUSEL0_CH14_Pos) +#define TAL_DMACPUSEL0_CH14(value) (TAL_DMACPUSEL0_CH14_Msk & ((value) << TAL_DMACPUSEL0_CH14_Pos)) +#define TAL_DMACPUSEL0_CH15_Pos 30 /**< \brief (TAL_DMACPUSEL0) DMA Channel 15 Interrupt CPU Select */ +#define TAL_DMACPUSEL0_CH15_Msk (_U_(0x1) << TAL_DMACPUSEL0_CH15_Pos) +#define TAL_DMACPUSEL0_CH15(value) (TAL_DMACPUSEL0_CH15_Msk & ((value) << TAL_DMACPUSEL0_CH15_Pos)) +#define TAL_DMACPUSEL0_MASK _U_(0x55555555) /**< \brief (TAL_DMACPUSEL0) MASK Register */ + +/* -------- TAL_DMACPUSEL1 : (TAL Offset: 0x114) (R/W 32) DMA Channel Interrupts CPU Select 1 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CH16:1; /*!< bit: 0 DMA Channel 16 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 1 Reserved */ + uint32_t CH17:1; /*!< bit: 2 DMA Channel 17 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 3 Reserved */ + uint32_t CH18:1; /*!< bit: 4 DMA Channel 18 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 5 Reserved */ + uint32_t CH19:1; /*!< bit: 6 DMA Channel 19 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t CH20:1; /*!< bit: 8 DMA Channel 20 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 9 Reserved */ + uint32_t CH21:1; /*!< bit: 10 DMA Channel 21 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 11 Reserved */ + uint32_t CH22:1; /*!< bit: 12 DMA Channel 22 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 13 Reserved */ + uint32_t CH23:1; /*!< bit: 14 DMA Channel 23 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 15 Reserved */ + uint32_t CH24:1; /*!< bit: 16 DMA Channel 24 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 17 Reserved */ + uint32_t CH25:1; /*!< bit: 18 DMA Channel 25 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 19 Reserved */ + uint32_t CH26:1; /*!< bit: 20 DMA Channel 26 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 21 Reserved */ + uint32_t CH27:1; /*!< bit: 22 DMA Channel 27 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 23 Reserved */ + uint32_t CH28:1; /*!< bit: 24 DMA Channel 28 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 25 Reserved */ + uint32_t CH29:1; /*!< bit: 26 DMA Channel 29 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 27 Reserved */ + uint32_t CH30:1; /*!< bit: 28 DMA Channel 30 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 29 Reserved */ + uint32_t CH31:1; /*!< bit: 30 DMA Channel 31 Interrupt CPU Select */ + uint32_t :1; /*!< bit: 31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} TAL_DMACPUSEL1_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |