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Diffstat (limited to 'lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/sdhc.h')
| -rw-r--r-- | lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/sdhc.h | 2599 |
1 files changed, 2599 insertions, 0 deletions
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/sdhc.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/sdhc.h new file mode 100644 index 0000000000..a42b9fc560 --- /dev/null +++ b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/sdhc.h @@ -0,0 +1,2599 @@ +/** + * \file + * + * \brief Component description for SDHC + * + * Copyright (c) 2017 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD51_SDHC_COMPONENT_ +#define _SAMD51_SDHC_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR SDHC */ +/* ========================================================================== */ +/** \addtogroup SAMD51_SDHC SD/MMC Host Controller */ +/*@{*/ + +#define SDHC_U2011 +#define REV_SDHC 0x183 + +/* -------- SDHC_SSAR : (SDHC Offset: 0x000) (R/W 32) SDMA System Address / Argument 2 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { // CMD23 mode + uint32_t ARG2:32; /*!< bit: 0..31 Argument 2 */ + } CMD23; /*!< Structure used for CMD23 */ + struct { + uint32_t ADDR:32; /*!< bit: 0..31 SDMA System Address */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} SDHC_SSAR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SDHC_SSAR_OFFSET 0x000 /**< \brief (SDHC_SSAR offset) SDMA System Address / Argument 2 */ +#define SDHC_SSAR_RESETVALUE _U_(0x00000000) /**< \brief (SDHC_SSAR reset_value) SDMA System Address / Argument 2 */ + +// CMD23 mode +#define SDHC_SSAR_CMD23_ARG2_Pos 0 /**< \brief (SDHC_SSAR_CMD23) Argument 2 */ +#define SDHC_SSAR_CMD23_ARG2_Msk (_U_(0xFFFFFFFF) << SDHC_SSAR_CMD23_ARG2_Pos) +#define SDHC_SSAR_CMD23_ARG2(value) (SDHC_SSAR_CMD23_ARG2_Msk & ((value) << SDHC_SSAR_CMD23_ARG2_Pos)) +#define SDHC_SSAR_CMD23_MASK _U_(0xFFFFFFFF) /**< \brief (SDHC_SSAR_CMD23) MASK Register */ + +#define SDHC_SSAR_ADDR_Pos 0 /**< \brief (SDHC_SSAR) SDMA System Address */ +#define SDHC_SSAR_ADDR_Msk (_U_(0xFFFFFFFF) << SDHC_SSAR_ADDR_Pos) +#define SDHC_SSAR_ADDR(value) (SDHC_SSAR_ADDR_Msk & ((value) << SDHC_SSAR_ADDR_Pos)) +#define SDHC_SSAR_MASK _U_(0xFFFFFFFF) /**< \brief (SDHC_SSAR) MASK Register */ + +/* -------- SDHC_BSR : (SDHC Offset: 0x004) (R/W 16) Block Size -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t BLOCKSIZE:10; /*!< bit: 0.. 9 Transfer Block Size */ + uint16_t :2; /*!< bit: 10..11 Reserved */ + uint16_t BOUNDARY:3; /*!< bit: 12..14 SDMA Buffer Boundary */ + uint16_t :1; /*!< bit: 15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} SDHC_BSR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SDHC_BSR_OFFSET 0x004 /**< \brief (SDHC_BSR offset) Block Size */ +#define SDHC_BSR_RESETVALUE _U_(0x0000) /**< \brief (SDHC_BSR reset_value) Block Size */ + +#define SDHC_BSR_BLOCKSIZE_Pos 0 /**< \brief (SDHC_BSR) Transfer Block Size */ +#define SDHC_BSR_BLOCKSIZE_Msk (_U_(0x3FF) << SDHC_BSR_BLOCKSIZE_Pos) +#define SDHC_BSR_BLOCKSIZE(value) (SDHC_BSR_BLOCKSIZE_Msk & ((value) << SDHC_BSR_BLOCKSIZE_Pos)) +#define SDHC_BSR_BOUNDARY_Pos 12 /**< \brief (SDHC_BSR) SDMA Buffer Boundary */ +#define SDHC_BSR_BOUNDARY_Msk (_U_(0x7) << SDHC_BSR_BOUNDARY_Pos) +#define SDHC_BSR_BOUNDARY(value) (SDHC_BSR_BOUNDARY_Msk & ((value) << SDHC_BSR_BOUNDARY_Pos)) +#define SDHC_BSR_BOUNDARY_4K_Val _U_(0x0) /**< \brief (SDHC_BSR) 4k bytes */ +#define SDHC_BSR_BOUNDARY_8K_Val _U_(0x1) /**< \brief (SDHC_BSR) 8k bytes */ +#define SDHC_BSR_BOUNDARY_16K_Val _U_(0x2) /**< \brief (SDHC_BSR) 16k bytes */ +#define SDHC_BSR_BOUNDARY_32K_Val _U_(0x3) /**< \brief (SDHC_BSR) 32k bytes */ +#define SDHC_BSR_BOUNDARY_64K_Val _U_(0x4) /**< \brief (SDHC_BSR) 64k bytes */ +#define SDHC_BSR_BOUNDARY_128K_Val _U_(0x5) /**< \brief (SDHC_BSR) 128k bytes */ +#define SDHC_BSR_BOUNDARY_256K_Val _U_(0x6) /**< \brief (SDHC_BSR) 256k bytes */ +#define SDHC_BSR_BOUNDARY_512K_Val _U_(0x7) /**< \brief (SDHC_BSR) 512k bytes */ +#define SDHC_BSR_BOUNDARY_4K (SDHC_BSR_BOUNDARY_4K_Val << SDHC_BSR_BOUNDARY_Pos) +#define SDHC_BSR_BOUNDARY_8K (SDHC_BSR_BOUNDARY_8K_Val << SDHC_BSR_BOUNDARY_Pos) +#define SDHC_BSR_BOUNDARY_16K (SDHC_BSR_BOUNDARY_16K_Val << SDHC_BSR_BOUNDARY_Pos) +#define SDHC_BSR_BOUNDARY_32K (SDHC_BSR_BOUNDARY_32K_Val << SDHC_BSR_BOUNDARY_Pos) +#define SDHC_BSR_BOUNDARY_64K (SDHC_BSR_BOUNDARY_64K_Val << SDHC_BSR_BOUNDARY_Pos) +#define SDHC_BSR_BOUNDARY_128K (SDHC_BSR_BOUNDARY_128K_Val << SDHC_BSR_BOUNDARY_Pos) +#define SDHC_BSR_BOUNDARY_256K (SDHC_BSR_BOUNDARY_256K_Val << SDHC_BSR_BOUNDARY_Pos) +#define SDHC_BSR_BOUNDARY_512K (SDHC_BSR_BOUNDARY_512K_Val << SDHC_BSR_BOUNDARY_Pos) +#define SDHC_BSR_MASK _U_(0x73FF) /**< \brief (SDHC_BSR) MASK Register */ + +/* -------- SDHC_BCR : (SDHC Offset: 0x006) (R/W 16) Block Count -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t BCNT:16; /*!< bit: 0..15 Blocks Count for Current Transfer */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} SDHC_BCR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SDHC_BCR_OFFSET 0x006 /**< \brief (SDHC_BCR offset) Block Count */ +#define SDHC_BCR_RESETVALUE _U_(0x0000) /**< \brief (SDHC_BCR reset_value) Block Count */ + +#define SDHC_BCR_BCNT_Pos 0 /**< \brief (SDHC_BCR) Blocks Count for Current Transfer */ +#define SDHC_BCR_BCNT_Msk (_U_(0xFFFF) << SDHC_BCR_BCNT_Pos) +#define SDHC_BCR_BCNT(value) (SDHC_BCR_BCNT_Msk & ((value) << SDHC_BCR_BCNT_Pos)) +#define SDHC_BCR_MASK _U_(0xFFFF) /**< \brief (SDHC_BCR) MASK Register */ + +/* -------- SDHC_ARG1R : (SDHC Offset: 0x008) (R/W 32) Argument 1 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ARG:32; /*!< bit: 0..31 Argument 1 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} SDHC_ARG1R_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SDHC_ARG1R_OFFSET 0x008 /**< \brief (SDHC_ARG1R offset) Argument 1 */ +#define SDHC_ARG1R_RESETVALUE _U_(0x00000000) /**< \brief (SDHC_ARG1R reset_value) Argument 1 */ + +#define SDHC_ARG1R_ARG_Pos 0 /**< \brief (SDHC_ARG1R) Argument 1 */ +#define SDHC_ARG1R_ARG_Msk (_U_(0xFFFFFFFF) << SDHC_ARG1R_ARG_Pos) +#define SDHC_ARG1R_ARG(value) (SDHC_ARG1R_ARG_Msk & ((value) << SDHC_ARG1R_ARG_Pos)) +#define SDHC_ARG1R_MASK _U_(0xFFFFFFFF) /**< \brief (SDHC_ARG1R) MASK Register */ + +/* -------- SDHC_TMR : (SDHC Offset: 0x00C) (R/W 16) Transfer Mode -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t DMAEN:1; /*!< bit: 0 DMA Enable */ + uint16_t BCEN:1; /*!< bit: 1 Block Count Enable */ + uint16_t ACMDEN:2; /*!< bit: 2.. 3 Auto Command Enable */ + uint16_t DTDSEL:1; /*!< bit: 4 Data Transfer Direction Selection */ + uint16_t MSBSEL:1; /*!< bit: 5 Multi/Single Block Selection */ + uint16_t :10; /*!< bit: 6..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} SDHC_TMR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SDHC_TMR_OFFSET 0x00C /**< \brief (SDHC_TMR offset) Transfer Mode */ +#define SDHC_TMR_RESETVALUE _U_(0x0000) /**< \brief (SDHC_TMR reset_value) Transfer Mode */ + +#define SDHC_TMR_DMAEN_Pos 0 /**< \brief (SDHC_TMR) DMA Enable */ +#define SDHC_TMR_DMAEN (_U_(0x1) << SDHC_TMR_DMAEN_Pos) +#define SDHC_TMR_DMAEN_DISABLE_Val _U_(0x0) /**< \brief (SDHC_TMR) No data transfer or Non DMA data transfer */ +#define SDHC_TMR_DMAEN_ENABLE_Val _U_(0x1) /**< \brief (SDHC_TMR) DMA data transfer */ +#define SDHC_TMR_DMAEN_DISABLE (SDHC_TMR_DMAEN_DISABLE_Val << SDHC_TMR_DMAEN_Pos) +#define SDHC_TMR_DMAEN_ENABLE (SDHC_TMR_DMAEN_ENABLE_Val << SDHC_TMR_DMAEN_Pos) +#define SDHC_TMR_BCEN_Pos 1 /**< \brief (SDHC_TMR) Block Count Enable */ +#define SDHC_TMR_BCEN (_U_(0x1) << SDHC_TMR_BCEN_Pos) +#define SDHC_TMR_BCEN_DISABLE_Val _U_(0x0) /**< \brief (SDHC_TMR) Disable */ +#define SDHC_TMR_BCEN_ENABLE_Val _U_(0x1) /**< \brief (SDHC_TMR) Enable */ +#define SDHC_TMR_BCEN_DISABLE (SDHC_TMR_BCEN_DISABLE_Val << SDHC_TMR_BCEN_Pos) +#define SDHC_TMR_BCEN_ENABLE (SDHC_TMR_BCEN_ENABLE_Val << SDHC_TMR_BCEN_Pos) +#define SDHC_TMR_ACMDEN_Pos 2 /**< \brief (SDHC_TMR) Auto Command Enable */ +#define SDHC_TMR_ACMDEN_Msk (_U_(0x3) << SDHC_TMR_ACMDEN_Pos) +#define SDHC_TMR_ACMDEN(value) (SDHC_TMR_ACMDEN_Msk & ((value) << SDHC_TMR_ACMDEN_Pos)) +#define SDHC_TMR_ACMDEN_DISABLED_Val _U_(0x0) /**< \brief (SDHC_TMR) Auto Command Disabled */ +#define SDHC_TMR_ACMDEN_CMD12_Val _U_(0x1) /**< \brief (SDHC_TMR) Auto CMD12 Enable */ +#define SDHC_TMR_ACMDEN_CMD23_Val _U_(0x2) /**< \brief (SDHC_TMR) Auto CMD23 Enable */ +#define SDHC_TMR_ACMDEN_3_Val _U_(0x3) /**< \brief (SDHC_TMR) Reserved */ +#define SDHC_TMR_ACMDEN_DISABLED (SDHC_TMR_ACMDEN_DISABLED_Val << SDHC_TMR_ACMDEN_Pos) +#define SDHC_TMR_ACMDEN_CMD12 (SDHC_TMR_ACMDEN_CMD12_Val << SDHC_TMR_ACMDEN_Pos) +#define SDHC_TMR_ACMDEN_CMD23 (SDHC_TMR_ACMDEN_CMD23_Val << SDHC_TMR_ACMDEN_Pos) +#define SDHC_TMR_ACMDEN_3 (SDHC_TMR_ACMDEN_3_Val << SDHC_TMR_ACMDEN_Pos) +#define SDHC_TMR_DTDSEL_Pos 4 /**< \brief (SDHC_TMR) Data Transfer Direction Selection */ +#define SDHC_TMR_DTDSEL (_U_(0x1) << SDHC_TMR_DTDSEL_Pos) +#define SDHC_TMR_DTDSEL_WRITE_Val _U_(0x0) /**< \brief (SDHC_TMR) Write (Host to Card) */ +#define SDHC_TMR_DTDSEL_READ_Val _U_(0x1) /**< \brief (SDHC_TMR) Read (Card to Host) */ +#define SDHC_TMR_DTDSEL_WRITE (SDHC_TMR_DTDSEL_WRITE_Val << SDHC_TMR_DTDSEL_Pos) +#define SDHC_TMR_DTDSEL_READ (SDHC_TMR_DTDSEL_READ_Val << SDHC_TMR_DTDSEL_Pos) +#define SDHC_TMR_MSBSEL_Pos 5 /**< \brief (SDHC_TMR) Multi/Single Block Selection */ +#define SDHC_TMR_MSBSEL (_U_(0x1) << SDHC_TMR_MSBSEL_Pos) +#define SDHC_TMR_MSBSEL_SINGLE_Val _U_(0x0) /**< \brief (SDHC_TMR) Single Block */ +#define SDHC_TMR_MSBSEL_MULTIPLE_Val _U_(0x1) /**< \brief (SDHC_TMR) Multiple Block */ +#define SDHC_TMR_MSBSEL_SINGLE (SDHC_TMR_MSBSEL_SINGLE_Val << SDHC_TMR_MSBSEL_Pos) +#define SDHC_TMR_MSBSEL_MULTIPLE (SDHC_TMR_MSBSEL_MULTIPLE_Val << SDHC_TMR_MSBSEL_Pos) +#define SDHC_TMR_MASK _U_(0x003F) /**< \brief (SDHC_TMR) MASK Register */ + +/* -------- SDHC_CR : (SDHC Offset: 0x00E) (R/W 16) Command -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t RESPTYP:2; /*!< bit: 0.. 1 Response Type */ + uint16_t :1; /*!< bit: 2 Reserved */ + uint16_t CMDCCEN:1; /*!< bit: 3 Command CRC Check Enable */ + uint16_t CMDICEN:1; /*!< bit: 4 Command Index Check Enable */ + uint16_t DPSEL:1; /*!< bit: 5 Data Present Select */ + uint16_t CMDTYP:2; /*!< bit: 6.. 7 Command Type */ + uint16_t CMDIDX:6; /*!< bit: 8..13 Command Index */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} SDHC_CR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SDHC_CR_OFFSET 0x00E /**< \brief (SDHC_CR offset) Command */ +#define SDHC_CR_RESETVALUE _U_(0x0000) /**< \brief (SDHC_CR reset_value) Command */ + +#define SDHC_CR_RESPTYP_Pos 0 /**< \brief (SDHC_CR) Response Type */ +#define SDHC_CR_RESPTYP_Msk (_U_(0x3) << SDHC_CR_RESPTYP_Pos) +#define SDHC_CR_RESPTYP(value) (SDHC_CR_RESPTYP_Msk & ((value) << SDHC_CR_RESPTYP_Pos)) +#define SDHC_CR_RESPTYP_NONE_Val _U_(0x0) /**< \brief (SDHC_CR) No response */ +#define SDHC_CR_RESPTYP_136_BIT_Val _U_(0x1) /**< \brief (SDHC_CR) 136-bit response */ +#define SDHC_CR_RESPTYP_48_BIT_Val _U_(0x2) /**< \brief (SDHC_CR) 48-bit response */ +#define SDHC_CR_RESPTYP_48_BIT_BUSY_Val _U_(0x3) /**< \brief (SDHC_CR) 48-bit response check busy after response */ +#define SDHC_CR_RESPTYP_NONE (SDHC_CR_RESPTYP_NONE_Val << SDHC_CR_RESPTYP_Pos) +#define SDHC_CR_RESPTYP_136_BIT (SDHC_CR_RESPTYP_136_BIT_Val << SDHC_CR_RESPTYP_Pos) +#define SDHC_CR_RESPTYP_48_BIT (SDHC_CR_RESPTYP_48_BIT_Val << SDHC_CR_RESPTYP_Pos) +#define SDHC_CR_RESPTYP_48_BIT_BUSY (SDHC_CR_RESPTYP_48_BIT_BUSY_Val << SDHC_CR_RESPTYP_Pos) +#define SDHC_CR_CMDCCEN_Pos 3 /**< \brief (SDHC_CR) Command CRC Check Enable */ +#define SDHC_CR_CMDCCEN (_U_(0x1) << SDHC_CR_CMDCCEN_Pos) +#define SDHC_CR_CMDCCEN_DISABLE_Val _U_(0x0) /**< \brief (SDHC_CR) Disable */ +#define SDHC_CR_CMDCCEN_ENABLE_Val _U_(0x1) /**< \brief (SDHC_CR) Enable */ +#define SDHC_CR_CMDCCEN_DISABLE (SDHC_CR_CMDCCEN_DISABLE_Val << SDHC_CR_CMDCCEN_Pos) +#define SDHC_CR_CMDCCEN_ENABLE (SDHC_CR_CMDCCEN_ENABLE_Val << SDHC_CR_CMDCCEN_Pos) +#define SDHC_CR_CMDICEN_Pos 4 /**< \brief (SDHC_CR) Command Index Check Enable */ +#define SDHC_CR_CMDICEN (_U_(0x1) << SDHC_CR_CMDICEN_Pos) +#define SDHC_CR_CMDICEN_DISABLE_Val _U_(0x0) /**< \brief (SDHC_CR) Disable */ +#define SDHC_CR_CMDICEN_ENABLE_Val _U_(0x1) /**< \brief (SDHC_CR) Enable */ +#define SDHC_CR_CMDICEN_DISABLE (SDHC_CR_CMDICEN_DISABLE_Val << SDHC_CR_CMDICEN_Pos) +#define SDHC_CR_CMDICEN_ENABLE (SDHC_CR_CMDICEN_ENABLE_Val << SDHC_CR_CMDICEN_Pos) +#define SDHC_CR_DPSEL_Pos 5 /**< \brief (SDHC_CR) Data Present Select */ +#define SDHC_CR_DPSEL (_U_(0x1) << SDHC_CR_DPSEL_Pos) +#define SDHC_CR_DPSEL_NO_DATA_Val _U_(0x0) /**< \brief (SDHC_CR) No Data Present */ +#define SDHC_CR_DPSEL_DATA_Val _U_(0x1) /**< \brief (SDHC_CR) Data Present */ +#define SDHC_CR_DPSEL_NO_DATA (SDHC_CR_DPSEL_NO_DATA_Val << SDHC_CR_DPSEL_Pos) +#define SDHC_CR_DPSEL_DATA (SDHC_CR_DPSEL_DATA_Val << SDHC_CR_DPSEL_Pos) +#define SDHC_CR_CMDTYP_Pos 6 /**< \brief (SDHC_CR) Command Type */ +#define SDHC_CR_CMDTYP_Msk (_U_(0x3) << SDHC_CR_CMDTYP_Pos) +#define SDHC_CR_CMDTYP(value) (SDHC_CR_CMDTYP_Msk & ((value) << SDHC_CR_CMDTYP_Pos)) +#define SDHC_CR_CMDTYP_NORMAL_Val _U_(0x0) /**< \brief (SDHC_CR) Other commands */ +#define SDHC_CR_CMDTYP_SUSPEND_Val _U_(0x1) /**< \brief (SDHC_CR) CMD52 for writing Bus Suspend in CCCR */ +#define SDHC_CR_CMDTYP_RESUME_Val _U_(0x2) /**< \brief (SDHC_CR) CMD52 for writing Function Select in CCCR */ +#define SDHC_CR_CMDTYP_ABORT_Val _U_(0x3) /**< \brief (SDHC_CR) CMD12, CMD52 for writing I/O Abort in CCCR */ +#define SDHC_CR_CMDTYP_NORMAL (SDHC_CR_CMDTYP_NORMAL_Val << SDHC_CR_CMDTYP_Pos) +#define SDHC_CR_CMDTYP_SUSPEND (SDHC_CR_CMDTYP_SUSPEND_Val << SDHC_CR_CMDTYP_Pos) +#define SDHC_CR_CMDTYP_RESUME (SDHC_CR_CMDTYP_RESUME_Val << SDHC_CR_CMDTYP_Pos) +#define SDHC_CR_CMDTYP_ABORT (SDHC_CR_CMDTYP_ABORT_Val << SDHC_CR_CMDTYP_Pos) +#define SDHC_CR_CMDIDX_Pos 8 /**< \brief (SDHC_CR) Command Index */ +#define SDHC_CR_CMDIDX_Msk (_U_(0x3F) << SDHC_CR_CMDIDX_Pos) +#define SDHC_CR_CMDIDX(value) (SDHC_CR_CMDIDX_Msk & ((value) << SDHC_CR_CMDIDX_Pos)) +#define SDHC_CR_MASK _U_(0x3FFB) /**< \brief (SDHC_CR) MASK Register */ + +/* -------- SDHC_RR : (SDHC Offset: 0x010) (R/ 32) Response -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CMDRESP:32; /*!< bit: 0..31 Command Response */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} SDHC_RR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SDHC_RR_OFFSET 0x010 /**< \brief (SDHC_RR offset) Response */ +#define SDHC_RR_RESETVALUE _U_(0x00000000) /**< \brief (SDHC_RR reset_value) Response */ + +#define SDHC_RR_CMDRESP_Pos 0 /**< \brief (SDHC_RR) Command Response */ +#define SDHC_RR_CMDRESP_Msk (_U_(0xFFFFFFFF) << SDHC_RR_CMDRESP_Pos) +#define SDHC_RR_CMDRESP(value) (SDHC_RR_CMDRESP_Msk & ((value) << SDHC_RR_CMDRESP_Pos)) +#define SDHC_RR_MASK _U_(0xFFFFFFFF) /**< \brief (SDHC_RR) MASK Register */ + +/* -------- SDHC_BDPR : (SDHC Offset: 0x020) (R/W 32) Buffer Data Port -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t BUFDATA:32; /*!< bit: 0..31 Buffer Data */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} SDHC_BDPR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SDHC_BDPR_OFFSET 0x020 /**< \brief (SDHC_BDPR offset) Buffer Data Port */ +#define SDHC_BDPR_RESETVALUE _U_(0x00000000) /**< \brief (SDHC_BDPR reset_value) Buffer Data Port */ + +#define SDHC_BDPR_BUFDATA_Pos 0 /**< \brief (SDHC_BDPR) Buffer Data */ +#define SDHC_BDPR_BUFDATA_Msk (_U_(0xFFFFFFFF) << SDHC_BDPR_BUFDATA_Pos) +#define SDHC_BDPR_BUFDATA(value) (SDHC_BDPR_BUFDATA_Msk & ((value) << SDHC_BDPR_BUFDATA_Pos)) +#define SDHC_BDPR_MASK _U_(0xFFFFFFFF) /**< \brief (SDHC_BDPR) MASK Register */ + +/* -------- SDHC_PSR : (SDHC Offset: 0x024) (R/ 32) Present State -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CMDINHC:1; /*!< bit: 0 Command Inhibit (CMD) */ + uint32_t CMDINHD:1; /*!< bit: 1 Command Inhibit (DAT) */ + uint32_t DLACT:1; /*!< bit: 2 DAT Line Active */ + uint32_t RTREQ:1; /*!< bit: 3 Re-Tuning Request */ + uint32_t :4; /*!< bit: 4.. 7 Reserved */ + uint32_t WTACT:1; /*!< bit: 8 Write Transfer Active */ + uint32_t RTACT:1; /*!< bit: 9 Read Transfer Active */ + uint32_t BUFWREN:1; /*!< bit: 10 Buffer Write Enable */ + uint32_t BUFRDEN:1; /*!< bit: 11 Buffer Read Enable */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t CARDINS:1; /*!< bit: 16 Card Inserted */ + uint32_t CARDSS:1; /*!< bit: 17 Card State Stable */ + uint32_t CARDDPL:1; /*!< bit: 18 Card Detect Pin Level */ + uint32_t WRPPL:1; /*!< bit: 19 Write Protect Pin Level */ + uint32_t DATLL:4; /*!< bit: 20..23 DAT[3:0] Line Level */ + uint32_t CMDLL:1; /*!< bit: 24 CMD Line Level */ + uint32_t :7; /*!< bit: 25..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} SDHC_PSR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SDHC_PSR_OFFSET 0x024 /**< \brief (SDHC_PSR offset) Present State */ +#define SDHC_PSR_RESETVALUE _U_(0x00F80000) /**< \brief (SDHC_PSR reset_value) Present State */ + +#define SDHC_PSR_CMDINHC_Pos 0 /**< \brief (SDHC_PSR) Command Inhibit (CMD) */ +#define SDHC_PSR_CMDINHC (_U_(0x1) << SDHC_PSR_CMDINHC_Pos) +#define SDHC_PSR_CMDINHC_CAN_Val _U_(0x0) /**< \brief (SDHC_PSR) Can issue command using only CMD line */ +#define SDHC_PSR_CMDINHC_CANNOT_Val _U_(0x1) /**< \brief (SDHC_PSR) Cannot issue command */ +#define SDHC_PSR_CMDINHC_CAN (SDHC_PSR_CMDINHC_CAN_Val << SDHC_PSR_CMDINHC_Pos) +#define SDHC_PSR_CMDINHC_CANNOT (SDHC_PSR_CMDINHC_CANNOT_Val << SDHC_PSR_CMDINHC_Pos) +#define SDHC_PSR_CMDINHD_Pos 1 /**< \brief (SDHC_PSR) Command Inhibit (DAT) */ +#define SDHC_PSR_CMDINHD (_U_(0x1) << SDHC_PSR_CMDINHD_Pos) +#define SDHC_PSR_CMDINHD_CAN_Val _U_(0x0) /**< \brief (SDHC_PSR) Can issue command which uses the DAT line */ +#define SDHC_PSR_CMDINHD_CANNOT_Val _U_(0x1) /**< \brief (SDHC_PSR) Cannot issue command which uses the DAT line */ +#define SDHC_PSR_CMDINHD_CAN (SDHC_PSR_CMDINHD_CAN_Val << SDHC_PSR_CMDINHD_Pos) +#define SDHC_PSR_CMDINHD_CANNOT (SDHC_PSR_CMDINHD_CANNOT_Val << SDHC_PSR_CMDINHD_Pos) +#define SDHC_PSR_DLACT_Pos 2 /**< \brief (SDHC_PSR) DAT Line Active */ +#define SDHC_PSR_DLACT (_U_(0x1) << SDHC_PSR_DLACT_Pos) +#define SDHC_PSR_DLACT_INACTIVE_Val _U_(0x0) /**< \brief (SDHC_PSR) DAT Line Inactive */ +#define SDHC_PSR_DLACT_ACTIVE_Val _U_(0x1) /**< \brief (SDHC_PSR) DAT Line Active */ +#define SDHC_PSR_DLACT_INACTIVE (SDHC_PSR_DLACT_INACTIVE_Val << SDHC_PSR_DLACT_Pos) +#define SDHC_PSR_DLACT_ACTIVE (SDHC_PSR_DLACT_ACTIVE_Val << SDHC_PSR_DLACT_Pos) +#define SDHC_PSR_RTREQ_Pos 3 /**< \brief (SDHC_PSR) Re-Tuning Request */ +#define SDHC_PSR_RTREQ (_U_(0x1) << SDHC_PSR_RTREQ_Pos) +#define SDHC_PSR_RTREQ_OK_Val _U_(0x0) /**< \brief (SDHC_PSR) Fixed or well-tuned sampling clock */ +#define SDHC_PSR_RTREQ_REQUIRED_Val _U_(0x1) /**< \brief (SDHC_PSR) Sampling clock needs re-tuning */ +#define SDHC_PSR_RTREQ_OK (SDHC_PSR_RTREQ_OK_Val << SDHC_PSR_RTREQ_Pos) +#define SDHC_PSR_RTREQ_REQUIRED (SDHC_PSR_RTREQ_REQUIRED_Val << SDHC_PSR_RTREQ_Pos) +#define SDHC_PSR_WTACT_Pos 8 /**< \brief (SDHC_PSR) Write Transfer Active */ +#define SDHC_PSR_WTACT (_U_(0x1) << SDHC_PSR_WTACT_Pos) +#define SDHC_PSR_WTACT_NO_Val _U_(0x0) /**< \brief (SDHC_PSR) No valid data */ +#define SDHC_PSR_WTACT_YES_Val _U_(0x1) /**< \brief (SDHC_PSR) Transferring data */ +#define SDHC_PSR_WTACT_NO (SDHC_PSR_WTACT_NO_Val << SDHC_PSR_WTACT_Pos) +#define SDHC_PSR_WTACT_YES (SDHC_PSR_WTACT_YES_Val << SDHC_PSR_WTACT_Pos) +#define SDHC_PSR_RTACT_Pos 9 /**< \brief (SDHC_PSR) Read Transfer Active */ +#define SDHC_PSR_RTACT (_U_(0x1) << SDHC_PSR_RTACT_Pos) +#define SDHC_PSR_RTACT_NO_Val _U_(0x0) /**< \brief (SDHC_PSR) No valid data */ +#define SDHC_PSR_RTACT_YES_Val _U_(0x1) /**< \brief (SDHC_PSR) Transferring data */ +#define SDHC_PSR_RTACT_NO (SDHC_PSR_RTACT_NO_Val << SDHC_PSR_RTACT_Pos) +#define SDHC_PSR_RTACT_YES (SDHC_PSR_RTACT_YES_Val << SDHC_PSR_RTACT_Pos) +#define SDHC_PSR_BUFWREN_Pos 10 /**< \brief (SDHC_PSR) Buffer Write Enable */ +#define SDHC_PSR_BUFWREN (_U_(0x1) << SDHC_PSR_BUFWREN_Pos) +#define SDHC_PSR_BUFWREN_DISABLE_Val _U_(0x0) /**< \brief (SDHC_PSR) Write disable */ +#define SDHC_PSR_BUFWREN_ENABLE_Val _U_(0x1) /**< \brief (SDHC_PSR) Write enable */ +#define SDHC_PSR_BUFWREN_DISABLE (SDHC_PSR_BUFWREN_DISABLE_Val << SDHC_PSR_BUFWREN_Pos) +#define SDHC_PSR_BUFWREN_ENABLE (SDHC_PSR_BUFWREN_ENABLE_Val << SDHC_PSR_BUFWREN_Pos) +#define SDHC_PSR_BUFRDEN_Pos 11 /**< \brief (SDHC_PSR) Buffer Read Enable */ +#define SDHC_PSR_BUFRDEN (_U_(0x1) << SDHC_PSR_BUFRDEN_Pos) +#define SDHC_PSR_BUFRDEN_DISABLE_Val _U_(0x0) /**< \brief (SDHC_PSR) Read disable */ +#define SDHC_PSR_BUFRDEN_ENABLE_Val _U_(0x1) /**< \brief (SDHC_PSR) Read enable */ +#define SDHC_PSR_BUFRDEN_DISABLE (SDHC_PSR_BUFRDEN_DISABLE_Val << SDHC_PSR_BUFRDEN_Pos) +#define SDHC_PSR_BUFRDEN_ENABLE (SDHC_PSR_BUFRDEN_ENABLE_Val << SDHC_PSR_BUFRDEN_Pos) +#define SDHC_PSR_CARDINS_Pos 16 /**< \brief (SDHC_PSR) Card Inserted */ +#define SDHC_PSR_CARDINS (_U_(0x1) << SDHC_PSR_CARDINS_Pos) +#define SDHC_PSR_CARDINS_NO_Val _U_(0x0) /**< \brief (SDHC_PSR) Reset or Debouncing or No Card */ +#define SDHC_PSR_CARDINS_YES_Val _U_(0x1) /**< \brief (SDHC_PSR) Card inserted */ +#define SDHC_PSR_CARDINS_NO (SDHC_PSR_CARDINS_NO_Val << SDHC_PSR_CARDINS_Pos) +#define SDHC_PSR_CARDINS_YES (SDHC_PSR_CARDINS_YES_Val << SDHC_PSR_CARDINS_Pos) +#define SDHC_PSR_CARDSS_Pos 17 /**< \brief (SDHC_PSR) Card State Stable */ +#define SDHC_PSR_CARDSS (_U_(0x1) << SDHC_PSR_CARDSS_Pos) +#define SDHC_PSR_CARDSS_NO_Val _U_(0x0) /**< \brief (SDHC_PSR) Reset or Debouncing */ +#define SDHC_PSR_CARDSS_YES_Val _U_(0x1) /**< \brief (SDHC_PSR) No Card or Insered */ +#define SDHC_PSR_CARDSS_NO (SDHC_PSR_CARDSS_NO_Val << SDHC_PSR_CARDSS_Pos) +#define SDHC_PSR_CARDSS_YES (SDHC_PSR_CARDSS_YES_Val << SDHC_PSR_CARDSS_Pos) +#define SDHC_PSR_CARDDPL_Pos 18 /**< \brief (SDHC_PSR) Card Detect Pin Level */ +#define SDHC_PSR_CARDDPL (_U_(0x1) << SDHC_PSR_CARDDPL_Pos) +#define SDHC_PSR_CARDDPL_NO_Val _U_(0x0) /**< \brief (SDHC_PSR) No card present (SDCD#=1) */ +#define SDHC_PSR_CARDDPL_YES_Val _U_(0x1) /**< \brief (SDHC_PSR) Card present (SDCD#=0) */ +#define SDHC_PSR_CARDDPL_NO (SDHC_PSR_CARDDPL_NO_Val << SDHC_PSR_CARDDPL_Pos) +#define SDHC_PSR_CARDDPL_YES (SDHC_PSR_CARDDPL_YES_Val << SDHC_PSR_CARDDPL_Pos) +#define SDHC_PSR_WRPPL_Pos 19 /**< \brief (SDHC_PSR) Write Protect Pin Level */ +#define SDHC_PSR_WRPPL (_U_(0x1) << SDHC_PSR_WRPPL_Pos) +#define SDHC_PSR_WRPPL_PROTECTED_Val _U_(0x0) /**< \brief (SDHC_PSR) Write protected (SDWP#=0) */ +#define SDHC_PSR_WRPPL_ENABLED_Val _U_(0x1) /**< \brief (SDHC_PSR) Write enabled (SDWP#=1) */ +#define SDHC_PSR_WRPPL_PROTECTED (SDHC_PSR_WRPPL_PROTECTED_Val << SDHC_PSR_WRPPL_Pos) +#define SDHC_PSR_WRPPL_ENABLED (SDHC_PSR_WRPPL_ENABLED_Val << SDHC_PSR_WRPPL_Pos) +#define SDHC_PSR_DATLL_Pos 20 /**< \brief (SDHC_PSR) DAT[3:0] Line Level */ +#define SDHC_PSR_DATLL_Msk (_U_(0xF) << SDHC_PSR_DATLL_Pos) +#define SDHC_PSR_DATLL(value) (SDHC_PSR_DATLL_Msk & ((value) << SDHC_PSR_DATLL_Pos)) +#define SDHC_PSR_CMDLL_Pos 24 /**< \brief (SDHC_PSR) CMD Line Level */ +#define SDHC_PSR_CMDLL (_U_(0x1) << SDHC_PSR_CMDLL_Pos) +#define SDHC_PSR_MASK _U_(0x01FF0F0F) /**< \brief (SDHC_PSR) MASK Register */ + +/* -------- SDHC_HC1R : (SDHC Offset: 0x028) (R/W 8) Host Control 1 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t LEDCTRL:1; /*!< bit: 0 LED Control */ + uint8_t DW:1; /*!< bit: 1 Data Width */ + uint8_t HSEN:1; /*!< bit: 2 High Speed Enable */ + uint8_t DMASEL:2; /*!< bit: 3.. 4 DMA Select */ + uint8_t :1; /*!< bit: 5 Reserved */ + uint8_t CARDDTL:1; /*!< bit: 6 Card Detect Test Level */ + uint8_t CARDDSEL:1; /*!< bit: 7 Card Detect Signal Selection */ + } bit; /*!< Structure used for bit access */ + struct { // EMMC mode + uint8_t :1; /*!< bit: 0 Reserved */ + uint8_t DW:1; /*!< bit: 1 Data Width */ + uint8_t HSEN:1; /*!< bit: 2 High Speed Enable */ + uint8_t DMASEL:2; /*!< bit: 3.. 4 DMA Select */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } EMMC; /*!< Structure used for EMMC */ + uint8_t reg; /*!< Type used for register access */ +} SDHC_HC1R_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SDHC_HC1R_OFFSET 0x028 /**< \brief (SDHC_HC1R offset) Host Control 1 */ +#define SDHC_HC1R_RESETVALUE _U_(0xE00) /**< \brief (SDHC_HC1R reset_value) Host Control 1 */ + +#define SDHC_HC1R_LEDCTRL_Pos 0 /**< \brief (SDHC_HC1R) LED Control */ +#define SDHC_HC1R_LEDCTRL (_U_(0x1) << SDHC_HC1R_LEDCTRL_Pos) +#define SDHC_HC1R_LEDCTRL_OFF_Val _U_(0x0) /**< \brief (SDHC_HC1R) LED off */ +#define SDHC_HC1R_LEDCTRL_ON_Val _U_(0x1) /**< \brief (SDHC_HC1R) LED on */ +#define SDHC_HC1R_LEDCTRL_OFF (SDHC_HC1R_LEDCTRL_OFF_Val << SDHC_HC1R_LEDCTRL_Pos) +#define SDHC_HC1R_LEDCTRL_ON (SDHC_HC1R_LEDCTRL_ON_Val << SDHC_HC1R_LEDCTRL_Pos) +#define SDHC_HC1R_DW_Pos 1 /**< \brief (SDHC_HC1R) Data Width */ +#define SDHC_HC1R_DW (_U_(0x1) << SDHC_HC1R_DW_Pos) +#define SDHC_HC1R_DW_1BIT_Val _U_(0x0) /**< \brief (SDHC_HC1R) 1-bit mode */ +#define SDHC_HC1R_DW_4BIT_Val _U_(0x1) /**< \brief (SDHC_HC1R) 4-bit mode */ +#define SDHC_HC1R_DW_1BIT (SDHC_HC1R_DW_1BIT_Val << SDHC_HC1R_DW_Pos) +#define SDHC_HC1R_DW_4BIT (SDHC_HC1R_DW_4BIT_Val << SDHC_HC1R_DW_Pos) +#define SDHC_HC1R_HSEN_Pos 2 /**< \brief (SDHC_HC1R) High Speed Enable */ +#define SDHC_HC1R_HSEN (_U_(0x1) << SDHC_HC1R_HSEN_Pos) +#define SDHC_HC1R_HSEN_NORMAL_Val _U_(0x0) /**< \brief (SDHC_HC1R) Normal Speed mode */ +#define SDHC_HC1R_HSEN_HIGH_Val _U_(0x1) /**< \brief (SDHC_HC1R) High Speed mode */ +#define SDHC_HC1R_HSEN_NORMAL (SDHC_HC1R_HSEN_NORMAL_Val << SDHC_HC1R_HSEN_Pos) +#define SDHC_HC1R_HSEN_HIGH (SDHC_HC1R_HSEN_HIGH_Val << SDHC_HC1R_HSEN_Pos) +#define SDHC_HC1R_DMASEL_Pos 3 /**< \brief (SDHC_HC1R) DMA Select */ +#define SDHC_HC1R_DMASEL_Msk (_U_(0x3) << SDHC_HC1R_DMASEL_Pos) +#define SDHC_HC1R_DMASEL(value) (SDHC_HC1R_DMASEL_Msk & ((value) << SDHC_HC1R_DMASEL_Pos)) +#define SDHC_HC1R_DMASEL_SDMA_Val _U_(0x0) /**< \brief (SDHC_HC1R) SDMA is selected */ +#define SDHC_HC1R_DMASEL_1_Val _U_(0x1) /**< \brief (SDHC_HC1R) Reserved */ +#define SDHC_HC1R_DMASEL_32BIT_Val _U_(0x2) /**< \brief (SDHC_HC1R) 32-bit Address ADMA2 is selected */ +#define SDHC_HC1R_DMASEL_SDMA (SDHC_HC1R_DMASEL_SDMA_Val << SDHC_HC1R_DMASEL_Pos) +#define SDHC_HC1R_DMASEL_1 (SDHC_HC1R_DMASEL_1_Val << SDHC_HC1R_DMASEL_Pos) +#define SDHC_HC1R_DMASEL_32BIT (SDHC_HC1R_DMASEL_32BIT_Val << SDHC_HC1R_DMASEL_Pos) +#define SDHC_HC1R_CARDDTL_Pos 6 /**< \brief (SDHC_HC1R) Card Detect Test Level */ +#define SDHC_HC1R_CARDDTL (_U_(0x1) << SDHC_HC1R_CARDDTL_Pos) +#define SDHC_HC1R_CARDDTL_NO_Val _U_(0x0) /**< \brief (SDHC_HC1R) No Card */ +#define SDHC_HC1R_CARDDTL_YES_Val _U_(0x1) /**< \brief (SDHC_HC1R) Card Inserted */ +#define SDHC_HC1R_CARDDTL_NO (SDHC_HC1R_CARDDTL_NO_Val << SDHC_HC1R_CARDDTL_Pos) +#define SDHC_HC1R_CARDDTL_YES (SDHC_HC1R_CARDDTL_YES_Val << SDHC_HC1R_CARDDTL_Pos) +#define SDHC_HC1R_CARDDSEL_Pos 7 /**< \brief (SDHC_HC1R) Card Detect Signal Selection */ +#define SDHC_HC1R_CARDDSEL (_U_(0x1) << SDHC_HC1R_CARDDSEL_Pos) +#define SDHC_HC1R_CARDDSEL_NORMAL_Val _U_(0x0) /**< \brief (SDHC_HC1R) SDCD# is selected (for normal use) */ +#define SDHC_HC1R_CARDDSEL_TEST_Val _U_(0x1) /**< \brief (SDHC_HC1R) The Card Select Test Level is selected (for test purpose) */ +#define SDHC_HC1R_CARDDSEL_NORMAL (SDHC_HC1R_CARDDSEL_NORMAL_Val << SDHC_HC1R_CARDDSEL_Pos) +#define SDHC_HC1R_CARDDSEL_TEST (SDHC_HC1R_CARDDSEL_TEST_Val << SDHC_HC1R_CARDDSEL_Pos) +#define SDHC_HC1R_MASK _U_(0xDF) /**< \brief (SDHC_HC1R) MASK Register */ + +// EMMC mode +#define SDHC_HC1R_EMMC_DW_Pos 1 /**< \brief (SDHC_HC1R_EMMC) Data Width */ +#define SDHC_HC1R_EMMC_DW (_U_(0x1) << SDHC_HC1R_EMMC_DW_Pos) +#define SDHC_HC1R_EMMC_DW_1BIT_Val _U_(0x0) /**< \brief (SDHC_HC1R_EMMC) 1-bit mode */ +#define SDHC_HC1R_EMMC_DW_4BIT_Val _U_(0x1) /**< \brief (SDHC_HC1R_EMMC) 4-bit mode */ +#define SDHC_HC1R_EMMC_DW_1BIT (SDHC_HC1R_EMMC_DW_1BIT_Val << SDHC_HC1R_EMMC_DW_Pos) +#define SDHC_HC1R_EMMC_DW_4BIT (SDHC_HC1R_EMMC_DW_4BIT_Val << SDHC_HC1R_EMMC_DW_Pos) +#define SDHC_HC1R_EMMC_HSEN_Pos 2 /**< \brief (SDHC_HC1R_EMMC) High Speed Enable */ +#define SDHC_HC1R_EMMC_HSEN (_U_(0x1) << SDHC_HC1R_EMMC_HSEN_Pos) +#define SDHC_HC1R_EMMC_HSEN_NORMAL_Val _U_(0x0) /**< \brief (SDHC_HC1R_EMMC) Normal Speed mode */ +#define SDHC_HC1R_EMMC_HSEN_HIGH_Val _U_(0x1) /**< \brief (SDHC_HC1R_EMMC) High Speed mode */ +#define SDHC_HC1R_EMMC_HSEN_NORMAL (SDHC_HC1R_EMMC_HSEN_NORMAL_Val << SDHC_HC1R_EMMC_HSEN_Pos) +#define SDHC_HC1R_EMMC_HSEN_HIGH (SDHC_HC1R_EMMC_HSEN_HIGH_Val << SDHC_HC1R_EMMC_HSEN_Pos) +#define SDHC_HC1R_EMMC_DMASEL_Pos 3 /**< \brief (SDHC_HC1R_EMMC) DMA Select */ +#define SDHC_HC1R_EMMC_DMASEL_Msk (_U_(0x3) << SDHC_HC1R_EMMC_DMASEL_Pos) +#define SDHC_HC1R_EMMC_DMASEL(value) (SDHC_HC1R_EMMC_DMASEL_Msk & ((value) << SDHC_HC1R_EMMC_DMASEL_Pos)) +#define SDHC_HC1R_EMMC_DMASEL_SDMA_Val _U_(0x0) /**< \brief (SDHC_HC1R_EMMC) SDMA is selected */ +#define SDHC_HC1R_EMMC_DMASEL_1_Val _U_(0x1) /**< \brief (SDHC_HC1R_EMMC) Reserved */ +#define SDHC_HC1R_EMMC_DMASEL_32BIT_Val _U_(0x2) /**< \brief (SDHC_HC1R_EMMC) 32-bit Address ADMA2 is selected */ +#define SDHC_HC1R_EMMC_DMASEL_SDMA (SDHC_HC1R_EMMC_DMASEL_SDMA_Val << SDHC_HC1R_EMMC_DMASEL_Pos) +#define SDHC_HC1R_EMMC_DMASEL_1 (SDHC_HC1R_EMMC_DMASEL_1_Val << SDHC_HC1R_EMMC_DMASEL_Pos) +#define SDHC_HC1R_EMMC_DMASEL_32BIT (SDHC_HC1R_EMMC_DMASEL_32BIT_Val << SDHC_HC1R_EMMC_DMASEL_Pos) +#define SDHC_HC1R_EMMC_MASK _U_(0x1E) /**< \brief (SDHC_HC1R_EMMC) MASK Register */ + +/* -------- SDHC_PCR : (SDHC Offset: 0x029) (R/W 8) Power Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SDBPWR:1; /*!< bit: 0 SD Bus Power */ + uint8_t SDBVSEL:3; /*!< bit: 1.. 3 SD Bus Voltage Select */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} SDHC_PCR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SDHC_PCR_OFFSET 0x029 /**< \brief (SDHC_PCR offset) Power Control */ +#define SDHC_PCR_RESETVALUE _U_(0x0E) /**< \brief (SDHC_PCR reset_value) Power Control */ + +#define SDHC_PCR_SDBPWR_Pos 0 /**< \brief (SDHC_PCR) SD Bus Power */ +#define SDHC_PCR_SDBPWR (_U_(0x1) << SDHC_PCR_SDBPWR_Pos) +#define SDHC_PCR_SDBPWR_OFF_Val _U_(0x0) /**< \brief (SDHC_PCR) Power off */ +#define SDHC_PCR_SDBPWR_ON_Val _U_(0x1) /**< \brief (SDHC_PCR) Power on */ +#define SDHC_PCR_SDBPWR_OFF (SDHC_PCR_SDBPWR_OFF_Val << SDHC_PCR_SDBPWR_Pos) +#define SDHC_PCR_SDBPWR_ON (SDHC_PCR_SDBPWR_ON_Val << SDHC_PCR_SDBPWR_Pos) +#define SDHC_PCR_SDBVSEL_Pos 1 /**< \brief (SDHC_PCR) SD Bus Voltage Select */ +#define SDHC_PCR_SDBVSEL_Msk (_U_(0x7) << SDHC_PCR_SDBVSEL_Pos) +#define SDHC_PCR_SDBVSEL(value) (SDHC_PCR_SDBVSEL_Msk & ((value) << SDHC_PCR_SDBVSEL_Pos)) +#define SDHC_PCR_SDBVSEL_1V8_Val _U_(0x5) /**< \brief (SDHC_PCR) 1.8V (Typ.) */ +#define SDHC_PCR_SDBVSEL_3V0_Val _U_(0x6) /**< \brief (SDHC_PCR) 3.0V (Typ.) */ +#define SDHC_PCR_SDBVSEL_3V3_Val _U_(0x7) /**< \brief (SDHC_PCR) 3.3V (Typ.) */ +#define SDHC_PCR_SDBVSEL_1V8 (SDHC_PCR_SDBVSEL_1V8_Val << SDHC_PCR_SDBVSEL_Pos) +#define SDHC_PCR_SDBVSEL_3V0 (SDHC_PCR_SDBVSEL_3V0_Val << SDHC_PCR_SDBVSEL_Pos) +#define SDHC_PCR_SDBVSEL_3V3 (SDHC_PCR_SDBVSEL_3V3_Val << SDHC_PCR_SDBVSEL_Pos) +#define SDHC_PCR_MASK _U_(0x0F) /**< \brief (SDHC_PCR) MASK Register */ + +/* -------- SDHC_BGCR : (SDHC Offset: 0x02A) (R/W 8) Block Gap Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t STPBGR:1; /*!< bit: 0 Stop at Block Gap Request */ + uint8_t CONTR:1; /*!< bit: 1 Continue Request */ + uint8_t RWCTRL:1; /*!< bit: 2 Read Wait Control */ + uint8_t INTBG:1; /*!< bit: 3 Interrupt at Block Gap */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { // EMMC mode + uint8_t STPBGR:1; /*!< bit: 0 Stop at Block Gap Request */ + uint8_t CONTR:1; /*!< bit: 1 Continue Request */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } EMMC; /*!< Structure used for EMMC */ + uint8_t reg; /*!< Type used for register access */ +} SDHC_BGCR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SDHC_BGCR_OFFSET 0x02A /**< \brief (SDHC_BGCR offset) Block Gap Control */ +#define SDHC_BGCR_RESETVALUE _U_(0x00) /**< \brief (SDHC_BGCR reset_value) Block Gap Control */ + +#define SDHC_BGCR_STPBGR_Pos 0 /**< \brief (SDHC_BGCR) Stop at Block Gap Request */ +#define SDHC_BGCR_STPBGR (_U_(0x1) << SDHC_BGCR_STPBGR_Pos) +#define SDHC_BGCR_STPBGR_TRANSFER_Val _U_(0x0) /**< \brief (SDHC_BGCR) Transfer */ +#define SDHC_BGCR_STPBGR_STOP_Val _U_(0x1) /**< \brief (SDHC_BGCR) Stop */ +#define SDHC_BGCR_STPBGR_TRANSFER (SDHC_BGCR_STPBGR_TRANSFER_Val << SDHC_BGCR_STPBGR_Pos) +#define SDHC_BGCR_STPBGR_STOP (SDHC_BGCR_STPBGR_STOP_Val << SDHC_BGCR_STPBGR_Pos) +#define SDHC_BGCR_CONTR_Pos 1 /**< \brief (SDHC_BGCR) Continue Request */ +#define SDHC_BGCR_CONTR (_U_(0x1) << SDHC_BGCR_CONTR_Pos) +#define SDHC_BGCR_CONTR_GO_ON_Val _U_(0x0) /**< \brief (SDHC_BGCR) Not affected */ +#define SDHC_BGCR_CONTR_RESTART_Val _U_(0x1) /**< \brief (SDHC_BGCR) Restart */ +#define SDHC_BGCR_CONTR_GO_ON (SDHC_BGCR_CONTR_GO_ON_Val << SDHC_BGCR_CONTR_Pos) +#define SDHC_BGCR_CONTR_RESTART (SDHC_BGCR_CONTR_RESTART_Val << SDHC_BGCR_CONTR_Pos) +#define SDHC_BGCR_RWCTRL_Pos 2 /**< \brief (SDHC_BGCR) Read Wait Control */ +#define SDHC_BGCR_RWCTRL (_U_(0x1) << SDHC_BGCR_RWCTRL_Pos) +#define SDHC_BGCR_RWCTRL_DISABLE_Val _U_(0x0) /**< \brief (SDHC_BGCR) Disable Read Wait Control */ +#define SDHC_BGCR_RWCTRL_ENABLE_Val _U_(0x1) /**< \brief (SDHC_BGCR) Enable Read Wait Control */ +#define SDHC_BGCR_RWCTRL_DISABLE (SDHC_BGCR_RWCTRL_DISABLE_Val << SDHC_BGCR_RWCTRL_Pos) +#define SDHC_BGCR_RWCTRL_ENABLE (SDHC_BGCR_RWCTRL_ENABLE_Val << SDHC_BGCR_RWCTRL_Pos) +#define SDHC_BGCR_INTBG_Pos 3 /**< \brief (SDHC_BGCR) Interrupt at Block Gap */ +#define SDHC_BGCR_INTBG (_U_(0x1) << SDHC_BGCR_INTBG_Pos) +#define SDHC_BGCR_INTBG_DISABLED_Val _U_(0x0) /**< \brief (SDHC_BGCR) Disabled */ +#define SDHC_BGCR_INTBG_ENABLED_Val _U_(0x1) /**< \brief (SDHC_BGCR) Enabled */ +#define SDHC_BGCR_INTBG_DISABLED (SDHC_BGCR_INTBG_DISABLED_Val << SDHC_BGCR_INTBG_Pos) +#define SDHC_BGCR_INTBG_ENABLED (SDHC_BGCR_INTBG_ENABLED_Val << SDHC_BGCR_INTBG_Pos) +#define SDHC_BGCR_MASK _U_(0x0F) /**< \brief (SDHC_BGCR) MASK Register */ + +// EMMC mode +#define SDHC_BGCR_EMMC_STPBGR_Pos 0 /**< \brief (SDHC_BGCR_EMMC) Stop at Block Gap Request */ +#define SDHC_BGCR_EMMC_STPBGR (_U_(0x1) << SDHC_BGCR_EMMC_STPBGR_Pos) +#define SDHC_BGCR_EMMC_STPBGR_TRANSFER_Val _U_(0x0) /**< \brief (SDHC_BGCR_EMMC) Transfer */ +#define SDHC_BGCR_EMMC_STPBGR_STOP_Val _U_(0x1) /**< \brief (SDHC_BGCR_EMMC) Stop */ +#define SDHC_BGCR_EMMC_STPBGR_TRANSFER (SDHC_BGCR_EMMC_STPBGR_TRANSFER_Val << SDHC_BGCR_EMMC_STPBGR_Pos) +#define SDHC_BGCR_EMMC_STPBGR_STOP (SDHC_BGCR_EMMC_STPBGR_STOP_Val << SDHC_BGCR_EMMC_STPBGR_Pos) +#define SDHC_BGCR_EMMC_CONTR_Pos 1 /**< \brief (SDHC_BGCR_EMMC) Continue Request */ +#define SDHC_BGCR_EMMC_CONTR (_U_(0x1) << SDHC_BGCR_EMMC_CONTR_Pos) |