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Diffstat (limited to 'lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/dsu.h')
| -rw-r--r-- | lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/dsu.h | 1244 |
1 files changed, 1244 insertions, 0 deletions
diff --git a/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/dsu.h b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/dsu.h new file mode 100644 index 0000000000..43ae26d208 --- /dev/null +++ b/lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/dsu.h @@ -0,0 +1,1244 @@ +/** + * \file + * + * \brief Component description for DSU + * + * Copyright (c) 2017 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD51_DSU_COMPONENT_ +#define _SAMD51_DSU_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR DSU */ +/* ========================================================================== */ +/** \addtogroup SAMD51_DSU Device Service Unit */ +/*@{*/ + +#define DSU_U2410 +#define REV_DSU 0x100 + +/* -------- DSU_CTRL : (DSU Offset: 0x0000) ( /W 8) Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t :1; /*!< bit: 1 Reserved */ + uint8_t CRC:1; /*!< bit: 2 32-bit Cyclic Redundancy Code */ + uint8_t MBIST:1; /*!< bit: 3 Memory built-in self-test */ + uint8_t CE:1; /*!< bit: 4 Chip-Erase */ + uint8_t :1; /*!< bit: 5 Reserved */ + uint8_t ARR:1; /*!< bit: 6 Auxiliary Row Read */ + uint8_t SMSA:1; /*!< bit: 7 Start Memory Stream Access */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DSU_CTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DSU_CTRL_OFFSET 0x0000 /**< \brief (DSU_CTRL offset) Control */ +#define DSU_CTRL_RESETVALUE _U_(0x00) /**< \brief (DSU_CTRL reset_value) Control */ + +#define DSU_CTRL_SWRST_Pos 0 /**< \brief (DSU_CTRL) Software Reset */ +#define DSU_CTRL_SWRST (_U_(0x1) << DSU_CTRL_SWRST_Pos) +#define DSU_CTRL_CRC_Pos 2 /**< \brief (DSU_CTRL) 32-bit Cyclic Redundancy Code */ +#define DSU_CTRL_CRC (_U_(0x1) << DSU_CTRL_CRC_Pos) +#define DSU_CTRL_MBIST_Pos 3 /**< \brief (DSU_CTRL) Memory built-in self-test */ +#define DSU_CTRL_MBIST (_U_(0x1) << DSU_CTRL_MBIST_Pos) +#define DSU_CTRL_CE_Pos 4 /**< \brief (DSU_CTRL) Chip-Erase */ +#define DSU_CTRL_CE (_U_(0x1) << DSU_CTRL_CE_Pos) +#define DSU_CTRL_ARR_Pos 6 /**< \brief (DSU_CTRL) Auxiliary Row Read */ +#define DSU_CTRL_ARR (_U_(0x1) << DSU_CTRL_ARR_Pos) +#define DSU_CTRL_SMSA_Pos 7 /**< \brief (DSU_CTRL) Start Memory Stream Access */ +#define DSU_CTRL_SMSA (_U_(0x1) << DSU_CTRL_SMSA_Pos) +#define DSU_CTRL_MASK _U_(0xDD) /**< \brief (DSU_CTRL) MASK Register */ + +/* -------- DSU_STATUSA : (DSU Offset: 0x0001) (R/W 8) Status A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DONE:1; /*!< bit: 0 Done */ + uint8_t CRSTEXT:1; /*!< bit: 1 CPU Reset Phase Extension */ + uint8_t BERR:1; /*!< bit: 2 Bus Error */ + uint8_t FAIL:1; /*!< bit: 3 Failure */ + uint8_t PERR:1; /*!< bit: 4 Protection Error */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DSU_STATUSA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DSU_STATUSA_OFFSET 0x0001 /**< \brief (DSU_STATUSA offset) Status A */ +#define DSU_STATUSA_RESETVALUE _U_(0x00) /**< \brief (DSU_STATUSA reset_value) Status A */ + +#define DSU_STATUSA_DONE_Pos 0 /**< \brief (DSU_STATUSA) Done */ +#define DSU_STATUSA_DONE (_U_(0x1) << DSU_STATUSA_DONE_Pos) +#define DSU_STATUSA_CRSTEXT_Pos 1 /**< \brief (DSU_STATUSA) CPU Reset Phase Extension */ +#define DSU_STATUSA_CRSTEXT (_U_(0x1) << DSU_STATUSA_CRSTEXT_Pos) +#define DSU_STATUSA_BERR_Pos 2 /**< \brief (DSU_STATUSA) Bus Error */ +#define DSU_STATUSA_BERR (_U_(0x1) << DSU_STATUSA_BERR_Pos) +#define DSU_STATUSA_FAIL_Pos 3 /**< \brief (DSU_STATUSA) Failure */ +#define DSU_STATUSA_FAIL (_U_(0x1) << DSU_STATUSA_FAIL_Pos) +#define DSU_STATUSA_PERR_Pos 4 /**< \brief (DSU_STATUSA) Protection Error */ +#define DSU_STATUSA_PERR (_U_(0x1) << DSU_STATUSA_PERR_Pos) +#define DSU_STATUSA_MASK _U_(0x1F) /**< \brief (DSU_STATUSA) MASK Register */ + +/* -------- DSU_STATUSB : (DSU Offset: 0x0002) (R/ 8) Status B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t PROT:1; /*!< bit: 0 Protected */ + uint8_t DBGPRES:1; /*!< bit: 1 Debugger Present */ + uint8_t DCCD0:1; /*!< bit: 2 Debug Communication Channel 0 Dirty */ + uint8_t DCCD1:1; /*!< bit: 3 Debug Communication Channel 1 Dirty */ + uint8_t HPE:1; /*!< bit: 4 Hot-Plugging Enable */ + uint8_t CELCK:1; /*!< bit: 5 Chip Erase Locked */ + uint8_t TDCCD0:1; /*!< bit: 6 Test Debug Communication Channel 0 Dirty */ + uint8_t TDCCD1:1; /*!< bit: 7 Test Debug Communication Channel 1 Dirty */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t :2; /*!< bit: 0.. 1 Reserved */ + uint8_t DCCD:2; /*!< bit: 2.. 3 Debug Communication Channel x Dirty */ + uint8_t :2; /*!< bit: 4.. 5 Reserved */ + uint8_t TDCCD:2; /*!< bit: 6.. 7 Test Debug Communication Channel x Dirty */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} DSU_STATUSB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DSU_STATUSB_OFFSET 0x0002 /**< \brief (DSU_STATUSB offset) Status B */ +#define DSU_STATUSB_RESETVALUE _U_(0x00) /**< \brief (DSU_STATUSB reset_value) Status B */ + +#define DSU_STATUSB_PROT_Pos 0 /**< \brief (DSU_STATUSB) Protected */ +#define DSU_STATUSB_PROT (_U_(0x1) << DSU_STATUSB_PROT_Pos) +#define DSU_STATUSB_DBGPRES_Pos 1 /**< \brief (DSU_STATUSB) Debugger Present */ +#define DSU_STATUSB_DBGPRES (_U_(0x1) << DSU_STATUSB_DBGPRES_Pos) +#define DSU_STATUSB_DCCD0_Pos 2 /**< \brief (DSU_STATUSB) Debug Communication Channel 0 Dirty */ +#define DSU_STATUSB_DCCD0 (_U_(1) << DSU_STATUSB_DCCD0_Pos) +#define DSU_STATUSB_DCCD1_Pos 3 /**< \brief (DSU_STATUSB) Debug Communication Channel 1 Dirty */ +#define DSU_STATUSB_DCCD1 (_U_(1) << DSU_STATUSB_DCCD1_Pos) +#define DSU_STATUSB_DCCD_Pos 2 /**< \brief (DSU_STATUSB) Debug Communication Channel x Dirty */ +#define DSU_STATUSB_DCCD_Msk (_U_(0x3) << DSU_STATUSB_DCCD_Pos) +#define DSU_STATUSB_DCCD(value) (DSU_STATUSB_DCCD_Msk & ((value) << DSU_STATUSB_DCCD_Pos)) +#define DSU_STATUSB_HPE_Pos 4 /**< \brief (DSU_STATUSB) Hot-Plugging Enable */ +#define DSU_STATUSB_HPE (_U_(0x1) << DSU_STATUSB_HPE_Pos) +#define DSU_STATUSB_CELCK_Pos 5 /**< \brief (DSU_STATUSB) Chip Erase Locked */ +#define DSU_STATUSB_CELCK (_U_(0x1) << DSU_STATUSB_CELCK_Pos) +#define DSU_STATUSB_TDCCD0_Pos 6 /**< \brief (DSU_STATUSB) Test Debug Communication Channel 0 Dirty */ +#define DSU_STATUSB_TDCCD0 (_U_(1) << DSU_STATUSB_TDCCD0_Pos) +#define DSU_STATUSB_TDCCD1_Pos 7 /**< \brief (DSU_STATUSB) Test Debug Communication Channel 1 Dirty */ +#define DSU_STATUSB_TDCCD1 (_U_(1) << DSU_STATUSB_TDCCD1_Pos) +#define DSU_STATUSB_TDCCD_Pos 6 /**< \brief (DSU_STATUSB) Test Debug Communication Channel x Dirty */ +#define DSU_STATUSB_TDCCD_Msk (_U_(0x3) << DSU_STATUSB_TDCCD_Pos) +#define DSU_STATUSB_TDCCD(value) (DSU_STATUSB_TDCCD_Msk & ((value) << DSU_STATUSB_TDCCD_Pos)) +#define DSU_STATUSB_MASK _U_(0xFF) /**< \brief (DSU_STATUSB) MASK Register */ + +/* -------- DSU_ADDR : (DSU Offset: 0x0004) (R/W 32) Address -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t AMOD:2; /*!< bit: 0.. 1 Access Mode */ + uint32_t ADDR:30; /*!< bit: 2..31 Address */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DSU_ADDR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DSU_ADDR_OFFSET 0x0004 /**< \brief (DSU_ADDR offset) Address */ +#define DSU_ADDR_RESETVALUE _U_(0x00000000) /**< \brief (DSU_ADDR reset_value) Address */ + +#define DSU_ADDR_AMOD_Pos 0 /**< \brief (DSU_ADDR) Access Mode */ +#define DSU_ADDR_AMOD_Msk (_U_(0x3) << DSU_ADDR_AMOD_Pos) +#define DSU_ADDR_AMOD(value) (DSU_ADDR_AMOD_Msk & ((value) << DSU_ADDR_AMOD_Pos)) +#define DSU_ADDR_ADDR_Pos 2 /**< \brief (DSU_ADDR) Address */ +#define DSU_ADDR_ADDR_Msk (_U_(0x3FFFFFFF) << DSU_ADDR_ADDR_Pos) +#define DSU_ADDR_ADDR(value) (DSU_ADDR_ADDR_Msk & ((value) << DSU_ADDR_ADDR_Pos)) +#define DSU_ADDR_MASK _U_(0xFFFFFFFF) /**< \brief (DSU_ADDR) MASK Register */ + +/* -------- DSU_LENGTH : (DSU Offset: 0x0008) (R/W 32) Length -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :2; /*!< bit: 0.. 1 Reserved */ + uint32_t LENGTH:30; /*!< bit: 2..31 Length */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DSU_LENGTH_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DSU_LENGTH_OFFSET 0x0008 /**< \brief (DSU_LENGTH offset) Length */ +#define DSU_LENGTH_RESETVALUE _U_(0x00000000) /**< \brief (DSU_LENGTH reset_value) Length */ + +#define DSU_LENGTH_LENGTH_Pos 2 /**< \brief (DSU_LENGTH) Length */ +#define DSU_LENGTH_LENGTH_Msk (_U_(0x3FFFFFFF) << DSU_LENGTH_LENGTH_Pos) +#define DSU_LENGTH_LENGTH(value) (DSU_LENGTH_LENGTH_Msk & ((value) << DSU_LENGTH_LENGTH_Pos)) +#define DSU_LENGTH_MASK _U_(0xFFFFFFFC) /**< \brief (DSU_LENGTH) MASK Register */ + +/* -------- DSU_DATA : (DSU Offset: 0x000C) (R/W 32) Data -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t DATA:32; /*!< bit: 0..31 Data */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DSU_DATA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DSU_DATA_OFFSET 0x000C /**< \brief (DSU_DATA offset) Data */ +#define DSU_DATA_RESETVALUE _U_(0x00000000) /**< \brief (DSU_DATA reset_value) Data */ + +#define DSU_DATA_DATA_Pos 0 /**< \brief (DSU_DATA) Data */ +#define DSU_DATA_DATA_Msk (_U_(0xFFFFFFFF) << DSU_DATA_DATA_Pos) +#define DSU_DATA_DATA(value) (DSU_DATA_DATA_Msk & ((value) << DSU_DATA_DATA_Pos)) +#define DSU_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (DSU_DATA) MASK Register */ + +/* -------- DSU_DCC : (DSU Offset: 0x0010) (R/W 32) Debug Communication Channel n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t DATA:32; /*!< bit: 0..31 Data */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DSU_DCC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DSU_DCC_OFFSET 0x0010 /**< \brief (DSU_DCC offset) Debug Communication Channel n */ +#define DSU_DCC_RESETVALUE _U_(0x00000000) /**< \brief (DSU_DCC reset_value) Debug Communication Channel n */ + +#define DSU_DCC_DATA_Pos 0 /**< \brief (DSU_DCC) Data */ +#define DSU_DCC_DATA_Msk (_U_(0xFFFFFFFF) << DSU_DCC_DATA_Pos) +#define DSU_DCC_DATA(value) (DSU_DCC_DATA_Msk & ((value) << DSU_DCC_DATA_Pos)) +#define DSU_DCC_MASK _U_(0xFFFFFFFF) /**< \brief (DSU_DCC) MASK Register */ + +/* -------- DSU_DID : (DSU Offset: 0x0018) (R/ 32) Device Identification -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t DEVSEL:8; /*!< bit: 0.. 7 Device Select */ + uint32_t REVISION:4; /*!< bit: 8..11 Revision Number */ + uint32_t DIE:4; /*!< bit: 12..15 Die Number */ + uint32_t SERIES:6; /*!< bit: 16..21 Series */ + uint32_t :1; /*!< bit: 22 Reserved */ + uint32_t FAMILY:5; /*!< bit: 23..27 Family */ + uint32_t PROCESSOR:4; /*!< bit: 28..31 Processor */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DSU_DID_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DSU_DID_OFFSET 0x0018 /**< \brief (DSU_DID offset) Device Identification */ + +#define DSU_DID_DEVSEL_Pos 0 /**< \brief (DSU_DID) Device Select */ +#define DSU_DID_DEVSEL_Msk (_U_(0xFF) << DSU_DID_DEVSEL_Pos) +#define DSU_DID_DEVSEL(value) (DSU_DID_DEVSEL_Msk & ((value) << DSU_DID_DEVSEL_Pos)) +#define DSU_DID_REVISION_Pos 8 /**< \brief (DSU_DID) Revision Number */ +#define DSU_DID_REVISION_Msk (_U_(0xF) << DSU_DID_REVISION_Pos) +#define DSU_DID_REVISION(value) (DSU_DID_REVISION_Msk & ((value) << DSU_DID_REVISION_Pos)) +#define DSU_DID_DIE_Pos 12 /**< \brief (DSU_DID) Die Number */ +#define DSU_DID_DIE_Msk (_U_(0xF) << DSU_DID_DIE_Pos) +#define DSU_DID_DIE(value) (DSU_DID_DIE_Msk & ((value) << DSU_DID_DIE_Pos)) +#define DSU_DID_SERIES_Pos 16 /**< \brief (DSU_DID) Series */ +#define DSU_DID_SERIES_Msk (_U_(0x3F) << DSU_DID_SERIES_Pos) +#define DSU_DID_SERIES(value) (DSU_DID_SERIES_Msk & ((value) << DSU_DID_SERIES_Pos)) +#define DSU_DID_SERIES_0_Val _U_(0x0) /**< \brief (DSU_DID) Cortex-M0+ processor, basic feature set */ +#define DSU_DID_SERIES_1_Val _U_(0x1) /**< \brief (DSU_DID) Cortex-M0+ processor, USB */ +#define DSU_DID_SERIES_0 (DSU_DID_SERIES_0_Val << DSU_DID_SERIES_Pos) +#define DSU_DID_SERIES_1 (DSU_DID_SERIES_1_Val << DSU_DID_SERIES_Pos) +#define DSU_DID_FAMILY_Pos 23 /**< \brief (DSU_DID) Family */ +#define DSU_DID_FAMILY_Msk (_U_(0x1F) << DSU_DID_FAMILY_Pos) +#define DSU_DID_FAMILY(value) (DSU_DID_FAMILY_Msk & ((value) << DSU_DID_FAMILY_Pos)) +#define DSU_DID_FAMILY_0_Val _U_(0x0) /**< \brief (DSU_DID) General purpose microcontroller */ +#define DSU_DID_FAMILY_1_Val _U_(0x1) /**< \brief (DSU_DID) PicoPower */ +#define DSU_DID_FAMILY_0 (DSU_DID_FAMILY_0_Val << DSU_DID_FAMILY_Pos) +#define DSU_DID_FAMILY_1 (DSU_DID_FAMILY_1_Val << DSU_DID_FAMILY_Pos) +#define DSU_DID_PROCESSOR_Pos 28 /**< \brief (DSU_DID) Processor */ +#define DSU_DID_PROCESSOR_Msk (_U_(0xF) << DSU_DID_PROCESSOR_Pos) +#define DSU_DID_PROCESSOR(value) (DSU_DID_PROCESSOR_Msk & ((value) << DSU_DID_PROCESSOR_Pos)) +#define DSU_DID_PROCESSOR_CM0P_Val _U_(0x1) /**< \brief (DSU_DID) Cortex-M0+ */ +#define DSU_DID_PROCESSOR_CM23_Val _U_(0x2) /**< \brief (DSU_DID) Cortex-M23 */ +#define DSU_DID_PROCESSOR_CM3_Val _U_(0x3) /**< \brief (DSU_DID) Cortex-M3 */ +#define DSU_DID_PROCESSOR_CM4_Val _U_(0x5) /**< \brief (DSU_DID) Cortex-M4 */ +#define DSU_DID_PROCESSOR_CM4F_Val _U_(0x6) /**< \brief (DSU_DID) Cortex-M4 with FPU */ +#define DSU_DID_PROCESSOR_CM33_Val _U_(0x7) /**< \brief (DSU_DID) Cortex-M33 */ +#define DSU_DID_PROCESSOR_CM0P (DSU_DID_PROCESSOR_CM0P_Val << DSU_DID_PROCESSOR_Pos) +#define DSU_DID_PROCESSOR_CM23 (DSU_DID_PROCESSOR_CM23_Val << DSU_DID_PROCESSOR_Pos) +#define DSU_DID_PROCESSOR_CM3 (DSU_DID_PROCESSOR_CM3_Val << DSU_DID_PROCESSOR_Pos) +#define DSU_DID_PROCESSOR_CM4 (DSU_DID_PROCESSOR_CM4_Val << DSU_DID_PROCESSOR_Pos) +#define DSU_DID_PROCESSOR_CM4F (DSU_DID_PROCESSOR_CM4F_Val << DSU_DID_PROCESSOR_Pos) +#define DSU_DID_PROCESSOR_CM33 (DSU_DID_PROCESSOR_CM33_Val << DSU_DID_PROCESSOR_Pos) +#define DSU_DID_MASK _U_(0xFFBFFFFF) /**< \brief (DSU_DID) MASK Register */ + +/* -------- DSU_CFG : (DSU Offset: 0x001C) (R/W 32) Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t LQOS:2; /*!< bit: 0.. 1 Latency Quality Of Service */ + uint32_t DCCDMALEVEL:2; /*!< bit: 2.. 3 DMA Trigger Level */ + uint32_t ETBRAMEN:1; /*!< bit: 4 Trace Control */ + uint32_t :27; /*!< bit: 5..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DSU_CFG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DSU_CFG_OFFSET 0x001C /**< \brief (DSU_CFG offset) Configuration */ +#define DSU_CFG_RESETVALUE _U_(0x00000002) /**< \brief (DSU_CFG reset_value) Configuration */ + +#define DSU_CFG_LQOS_Pos 0 /**< \brief (DSU_CFG) Latency Quality Of Service */ +#define DSU_CFG_LQOS_Msk (_U_(0x3) << DSU_CFG_LQOS_Pos) +#define DSU_CFG_LQOS(value) (DSU_CFG_LQOS_Msk & ((value) << DSU_CFG_LQOS_Pos)) +#define DSU_CFG_DCCDMALEVEL_Pos 2 /**< \brief (DSU_CFG) DMA Trigger Level */ +#define DSU_CFG_DCCDMALEVEL_Msk (_U_(0x3) << DSU_CFG_DCCDMALEVEL_Pos) +#define DSU_CFG_DCCDMALEVEL(value) (DSU_CFG_DCCDMALEVEL_Msk & ((value) << DSU_CFG_DCCDMALEVEL_Pos)) +#define DSU_CFG_DCCDMALEVEL_EMPTY_Val _U_(0x0) /**< \brief (DSU_CFG) Trigger rises when DCC is empty */ +#define DSU_CFG_DCCDMALEVEL_FULL_Val _U_(0x1) /**< \brief (DSU_CFG) Trigger rises when DCC is full */ +#define DSU_CFG_DCCDMALEVEL_EMPTY (DSU_CFG_DCCDMALEVEL_EMPTY_Val << DSU_CFG_DCCDMALEVEL_Pos) +#define DSU_CFG_DCCDMALEVEL_FULL (DSU_CFG_DCCDMALEVEL_FULL_Val << DSU_CFG_DCCDMALEVEL_Pos) +#define DSU_CFG_ETBRAMEN_Pos 4 /**< \brief (DSU_CFG) Trace Control */ +#define DSU_CFG_ETBRAMEN (_U_(0x1) << DSU_CFG_ETBRAMEN_Pos) +#define DSU_CFG_MASK _U_(0x0000001F) /**< \brief (DSU_CFG) MASK Register */ + +/* -------- DSU_MBCTRL : (DSU Offset: 0x0040) (R/W 32) MBIST Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 MBIST Software Reset */ + uint32_t ENABLE:1; /*!< bit: 1 MBIST Enable */ + uint32_t :30; /*!< bit: 2..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DSU_MBCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DSU_MBCTRL_OFFSET 0x0040 /**< \brief (DSU_MBCTRL offset) MBIST Control */ +#define DSU_MBCTRL_RESETVALUE _U_(0x00000000) /**< \brief (DSU_MBCTRL reset_value) MBIST Control */ + +#define DSU_MBCTRL_SWRST_Pos 0 /**< \brief (DSU_MBCTRL) MBIST Software Reset */ +#define DSU_MBCTRL_SWRST (_U_(0x1) << DSU_MBCTRL_SWRST_Pos) +#define DSU_MBCTRL_ENABLE_Pos 1 /**< \brief (DSU_MBCTRL) MBIST Enable */ +#define DSU_MBCTRL_ENABLE (_U_(0x1) << DSU_MBCTRL_ENABLE_Pos) +#define DSU_MBCTRL_MASK _U_(0x00000003) /**< \brief (DSU_MBCTRL) MASK Register */ + +/* -------- DSU_MBCONFIG : (DSU Offset: 0x0044) (R/W 32) MBIST Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ALGO:5; /*!< bit: 0.. 4 MBIST Algorithm */ + uint32_t :1; /*!< bit: 5 Reserved */ + uint32_t DEFRDMARGIN:1; /*!< bit: 6 Force Default Read Margin */ + uint32_t DBG:1; /*!< bit: 7 Enable Debug Mode */ + uint32_t :24; /*!< bit: 8..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DSU_MBCONFIG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DSU_MBCONFIG_OFFSET 0x0044 /**< \brief (DSU_MBCONFIG offset) MBIST Configuration */ +#define DSU_MBCONFIG_RESETVALUE _U_(0x00000000) /**< \brief (DSU_MBCONFIG reset_value) MBIST Configuration */ + +#define DSU_MBCONFIG_ALGO_Pos 0 /**< \brief (DSU_MBCONFIG) MBIST Algorithm */ +#define DSU_MBCONFIG_ALGO_Msk (_U_(0x1F) << DSU_MBCONFIG_ALGO_Pos) +#define DSU_MBCONFIG_ALGO(value) (DSU_MBCONFIG_ALGO_Msk & ((value) << DSU_MBCONFIG_ALGO_Pos)) +#define DSU_MBCONFIG_ALGO_MEMCLEAR_Val _U_(0x0) /**< \brief (DSU_MBCONFIG) Memory Clear (1n) */ +#define DSU_MBCONFIG_ALGO_VERIFY_Val _U_(0x1) /**< \brief (DSU_MBCONFIG) Memory Verify (1n) */ +#define DSU_MBCONFIG_ALGO_CLEARVER_Val _U_(0x2) /**< \brief (DSU_MBCONFIG) Memory Clear and Verify (2n) */ +#define DSU_MBCONFIG_ALGO_ADDR_DEC_Val _U_(0x3) /**< \brief (DSU_MBCONFIG) Address Decoder (2n) */ +#define DSU_MBCONFIG_ALGO_MARCH_LR_Val _U_(0x4) /**< \brief (DSU_MBCONFIG) March LR (14n) */ +#define DSU_MBCONFIG_ALGO_MARCH_SR_Val _U_(0x5) /**< \brief (DSU_MBCONFIG) March SR (14n) */ +#define DSU_MBCONFIG_ALGO_MARCH_SS_Val _U_(0x6) /**< \brief (DSU_MBCONFIG) March SS (22n) */ +#define DSU_MBCONFIG_ALGO_CRC_UP_Val _U_(0x8) /**< \brief (DSU_MBCONFIG) CRC increasing address (1n) */ +#define DSU_MBCONFIG_ALGO_CRC_DOWN_Val _U_(0x9) /**< \brief (DSU_MBCONFIG) CRC decreasing address (1n) */ +#define DSU_MBCONFIG_ALGO_MEMCLEAR (DSU_MBCONFIG_ALGO_MEMCLEAR_Val << DSU_MBCONFIG_ALGO_Pos) +#define DSU_MBCONFIG_ALGO_VERIFY (DSU_MBCONFIG_ALGO_VERIFY_Val << DSU_MBCONFIG_ALGO_Pos) +#define DSU_MBCONFIG_ALGO_CLEARVER (DSU_MBCONFIG_ALGO_CLEARVER_Val << DSU_MBCONFIG_ALGO_Pos) +#define DSU_MBCONFIG_ALGO_ADDR_DEC (DSU_MBCONFIG_ALGO_ADDR_DEC_Val << DSU_MBCONFIG_ALGO_Pos) +#define DSU_MBCONFIG_ALGO_MARCH_LR (DSU_MBCONFIG_ALGO_MARCH_LR_Val << DSU_MBCONFIG_ALGO_Pos) +#define DSU_MBCONFIG_ALGO_MARCH_SR (DSU_MBCONFIG_ALGO_MARCH_SR_Val << DSU_MBCONFIG_ALGO_Pos) +#define DSU_MBCONFIG_ALGO_MARCH_SS (DSU_MBCONFIG_ALGO_MARCH_SS_Val << DSU_MBCONFIG_ALGO_Pos) +#define DSU_MBCONFIG_ALGO_CRC_UP (DSU_MBCONFIG_ALGO_CRC_UP_Val << DSU_MBCONFIG_ALGO_Pos) +#define DSU_MBCONFIG_ALGO_CRC_DOWN (DSU_MBCONFIG_ALGO_CRC_DOWN_Val << DSU_MBCONFIG_ALGO_Pos) +#define DSU_MBCONFIG_DEFRDMARGIN_Pos 6 /**< \brief (DSU_MBCONFIG) Force Default Read Margin */ +#define DSU_MBCONFIG_DEFRDMARGIN (_U_(0x1) << DSU_MBCONFIG_DEFRDMARGIN_Pos) +#define DSU_MBCONFIG_DBG_Pos 7 /**< \brief (DSU_MBCONFIG) Enable Debug Mode */ +#define DSU_MBCONFIG_DBG (_U_(0x1) << DSU_MBCONFIG_DBG_Pos) +#define DSU_MBCONFIG_MASK _U_(0x000000DF) /**< \brief (DSU_MBCONFIG) MASK Register */ + +/* -------- DSU_MBWORD : (DSU Offset: 0x0048) (R/W 32) MBIST Background Word -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t DATA:32; /*!< bit: 0..31 MBIST Background Word */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DSU_MBWORD_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DSU_MBWORD_OFFSET 0x0048 /**< \brief (DSU_MBWORD offset) MBIST Background Word */ +#define DSU_MBWORD_RESETVALUE _U_(0x00000000) /**< \brief (DSU_MBWORD reset_value) MBIST Background Word */ + +#define DSU_MBWORD_DATA_Pos 0 /**< \brief (DSU_MBWORD) MBIST Background Word */ +#define DSU_MBWORD_DATA_Msk (_U_(0xFFFFFFFF) << DSU_MBWORD_DATA_Pos) +#define DSU_MBWORD_DATA(value) (DSU_MBWORD_DATA_Msk & ((value) << DSU_MBWORD_DATA_Pos)) +#define DSU_MBWORD_MASK _U_(0xFFFFFFFF) /**< \brief (DSU_MBWORD) MASK Register */ + +/* -------- DSU_MBGSTAT : (DSU Offset: 0x004C) (R/W 32) MBIST Global Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ALLDONE:1; /*!< bit: 0 MBIST Completed */ + uint32_t FAILED:1; /*!< bit: 1 MBIST Failed */ + uint32_t ERRINFO:1; /*!< bit: 2 MBIST Error Info Present */ + uint32_t CONFIGURED:1; /*!< bit: 3 MBIST Configuration Sent */ + uint32_t :28; /*!< bit: 4..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DSU_MBGSTAT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DSU_MBGSTAT_OFFSET 0x004C /**< \brief (DSU_MBGSTAT offset) MBIST Global Status */ +#define DSU_MBGSTAT_RESETVALUE _U_(0x00000000) /**< \brief (DSU_MBGSTAT reset_value) MBIST Global Status */ + +#define DSU_MBGSTAT_ALLDONE_Pos 0 /**< \brief (DSU_MBGSTAT) MBIST Completed */ +#define DSU_MBGSTAT_ALLDONE (_U_(0x1) << DSU_MBGSTAT_ALLDONE_Pos) +#define DSU_MBGSTAT_FAILED_Pos 1 /**< \brief (DSU_MBGSTAT) MBIST Failed */ +#define DSU_MBGSTAT_FAILED (_U_(0x1) << DSU_MBGSTAT_FAILED_Pos) +#define DSU_MBGSTAT_ERRINFO_Pos 2 /**< \brief (DSU_MBGSTAT) MBIST Error Info Present */ +#define DSU_MBGSTAT_ERRINFO (_U_(0x1) << DSU_MBGSTAT_ERRINFO_Pos) +#define DSU_MBGSTAT_CONFIGURED_Pos 3 /**< \brief (DSU_MBGSTAT) MBIST Configuration Sent */ +#define DSU_MBGSTAT_CONFIGURED (_U_(0x1) << DSU_MBGSTAT_CONFIGURED_Pos) +#define DSU_MBGSTAT_MASK _U_(0x0000000F) /**< \brief (DSU_MBGSTAT) MASK Register */ + +/* -------- DSU_MBDFAIL : (DSU Offset: 0x0050) (R/ 32) MBIST Fail Data -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t DATA:32; /*!< bit: 0..31 Error Data Read */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DSU_MBDFAIL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DSU_MBDFAIL_OFFSET 0x0050 /**< \brief (DSU_MBDFAIL offset) MBIST Fail Data */ +#define DSU_MBDFAIL_RESETVALUE _U_(0x00000000) /**< \brief (DSU_MBDFAIL reset_value) MBIST Fail Data */ + +#define DSU_MBDFAIL_DATA_Pos 0 /**< \brief (DSU_MBDFAIL) Error Data Read */ +#define DSU_MBDFAIL_DATA_Msk (_U_(0xFFFFFFFF) << DSU_MBDFAIL_DATA_Pos) +#define DSU_MBDFAIL_DATA(value) (DSU_MBDFAIL_DATA_Msk & ((value) << DSU_MBDFAIL_DATA_Pos)) +#define DSU_MBDFAIL_MASK _U_(0xFFFFFFFF) /**< \brief (DSU_MBDFAIL) MASK Register */ + +/* -------- DSU_MBDEXP : (DSU Offset: 0x0054) (R/ 32) MBIST Expected Data -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t DATA:32; /*!< bit: 0..31 Expected Data */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DSU_MBDEXP_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DSU_MBDEXP_OFFSET 0x0054 /**< \brief (DSU_MBDEXP offset) MBIST Expected Data */ +#define DSU_MBDEXP_RESETVALUE _U_(0x00000000) /**< \brief (DSU_MBDEXP reset_value) MBIST Expected Data */ + +#define DSU_MBDEXP_DATA_Pos 0 /**< \brief (DSU_MBDEXP) Expected Data */ +#define DSU_MBDEXP_DATA_Msk (_U_(0xFFFFFFFF) << DSU_MBDEXP_DATA_Pos) +#define DSU_MBDEXP_DATA(value) (DSU_MBDEXP_DATA_Msk & ((value) << DSU_MBDEXP_DATA_Pos)) +#define DSU_MBDEXP_MASK _U_(0xFFFFFFFF) /**< \brief (DSU_MBDEXP) MASK Register */ + +/* -------- DSU_MBAFAIL : (DSU Offset: 0x0058) (R/ 32) MBIST Fail Address -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ADDR:14; /*!< bit: 0..13 Error Address */ + uint32_t :18; /*!< bit: 14..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DSU_MBAFAIL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DSU_MBAFAIL_OFFSET 0x0058 /**< \brief (DSU_MBAFAIL offset) MBIST Fail Address */ +#define DSU_MBAFAIL_RESETVALUE _U_(0x00000000) /**< \brief (DSU_MBAFAIL reset_value) MBIST Fail Address */ + +#define DSU_MBAFAIL_ADDR_Pos 0 /**< \brief (DSU_MBAFAIL) Error Address */ +#define DSU_MBAFAIL_ADDR_Msk (_U_(0x3FFF) << DSU_MBAFAIL_ADDR_Pos) +#define DSU_MBAFAIL_ADDR(value) (DSU_MBAFAIL_ADDR_Msk & ((value) << DSU_MBAFAIL_ADDR_Pos)) +#define DSU_MBAFAIL_MASK _U_(0x00003FFF) /**< \brief (DSU_MBAFAIL) MASK Register */ + +/* -------- DSU_MBCONTEXT : (DSU Offset: 0x005C) (R/ 32) MBIST Fail Context -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SUBSTEP:5; /*!< bit: 0.. 4 Algorithm Sub-step */ + uint32_t STEP:5; /*!< bit: 5.. 9 Algorithm Step */ + uint32_t PORT:1; /*!< bit: 10 DPRAM Port Index */ + uint32_t :21; /*!< bit: 11..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DSU_MBCONTEXT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DSU_MBCONTEXT_OFFSET 0x005C /**< \brief (DSU_MBCONTEXT offset) MBIST Fail Context */ +#define DSU_MBCONTEXT_RESETVALUE _U_(0x00000000) /**< \brief (DSU_MBCONTEXT reset_value) MBIST Fail Context */ + +#define DSU_MBCONTEXT_SUBSTEP_Pos 0 /**< \brief (DSU_MBCONTEXT) Algorithm Sub-step */ +#define DSU_MBCONTEXT_SUBSTEP_Msk (_U_(0x1F) << DSU_MBCONTEXT_SUBSTEP_Pos) +#define DSU_MBCONTEXT_SUBSTEP(value) (DSU_MBCONTEXT_SUBSTEP_Msk & ((value) << DSU_MBCONTEXT_SUBSTEP_Pos)) +#define DSU_MBCONTEXT_SUBSTEP_R0_1_Val _U_(0x1) /**< \brief (DSU_MBCONTEXT) */ +#define DSU_MBCONTEXT_SUBSTEP_R1_1_Val _U_(0x3) /**< \brief (DSU_MBCONTEXT) */ +#define DSU_MBCONTEXT_SUBSTEP_R0_2_Val _U_(0x5) /**< \brief (DSU_MBCONTEXT) */ +#define DSU_MBCONTEXT_SUBSTEP_R1_2_Val _U_(0x7) /**< \brief (DSU_MBCONTEXT) */ +#define DSU_MBCONTEXT_SUBSTEP_R0_3_Val _U_(0x9) /**< \brief (DSU_MBCONTEXT) */ +#define DSU_MBCONTEXT_SUBSTEP_R1_3_Val _U_(0xB) /**< \brief (DSU_MBCONTEXT) */ +#define DSU_MBCONTEXT_SUBSTEP_R0_1 (DSU_MBCONTEXT_SUBSTEP_R0_1_Val << DSU_MBCONTEXT_SUBSTEP_Pos) +#define DSU_MBCONTEXT_SUBSTEP_R1_1 (DSU_MBCONTEXT_SUBSTEP_R1_1_Val << DSU_MBCONTEXT_SUBSTEP_Pos) +#define DSU_MBCONTEXT_SUBSTEP_R0_2 (DSU_MBCONTEXT_SUBSTEP_R0_2_Val << DSU_MBCONTEXT_SUBSTEP_Pos) +#define DSU_MBCONTEXT_SUBSTEP_R1_2 (DSU_MBCONTEXT_SUBSTEP_R1_2_Val << DSU_MBCONTEXT_SUBSTEP_Pos) +#define DSU_MBCONTEXT_SUBSTEP_R0_3 (DSU_MBCONTEXT_SUBSTEP_R0_3_Val << DSU_MBCONTEXT_SUBSTEP_Pos) +#define DSU_MBCONTEXT_SUBSTEP_R1_3 (DSU_MBCONTEXT_SUBSTEP_R1_3_Val << DSU_MBCONTEXT_SUBSTEP_Pos) +#define DSU_MBCONTEXT_STEP_Pos 5 /**< \brief (DSU_MBCONTEXT) Algorithm Step */ +#define DSU_MBCONTEXT_STEP_Msk (_U_(0x1F) << DSU_MBCONTEXT_STEP_Pos) +#define DSU_MBCONTEXT_STEP(value) (DSU_MBCONTEXT_STEP_Msk & ((value) << DSU_MBCONTEXT_STEP_Pos)) +#define DSU_MBCONTEXT_STEP_DOWN_R0W1_Val _U_(0x2) /**< \brief (DSU_MBCONTEXT) */ +#define DSU_MBCONTEXT_STEP_UP_R1W0R0W1_Val _U_(0x3) /**< \brief (DSU_MBCONTEXT) */ +#define DSU_MBCONTEXT_STEP_UP_R1W0_Val _U_(0x4) /**< \brief (DSU_MBCONTEXT) */ +#define DSU_MBCONTEXT_STEP_UP_R0W1R1W0_Val _U_(0x5) /**< \brief (DSU_MBCONTEXT) */ +#define DSU_MBCONTEXT_STEP_UP_R0_Val _U_(0x6) /**< \brief (DSU_MBCONTEXT) */ +#define DSU_MBCONTEXT_STEP_UP_R0R0W0R0W1_Val _U_(0x7) /**< \brief (DSU_MBCONTEXT) */ +#define DSU_MBCONTEXT_STEP_UP_R1R1W1R1W0_Val _U_(0x8) /**< \brief (DSU_MBCONTEXT) */ +#define DSU_MBCONTEXT_STEP_DOWN_R0R0W0R0W1_Val _U_(0x9) /**< \brief (DSU_MBCONTEXT) */ +#define DSU_MBCONTEXT_STEP_DOWN_R1R1W1R1W0_Val _U_(0xA) /**< \brief (DSU_MBCONTEXT) */ +#define DSU_MBCONTEXT_STEP_UP_R0R0_Val _U_(0xC) /**< \brief (DSU_MBCONTEXT) */ +#define DSU_MBCONTEXT_STEP_DOWN_R1W0R0W1_Val _U_(0xE) /**< \brief (DSU_MBCONTEXT) */ +#define DSU_MBCONTEXT_STEP_DOWN_R1R1_Val _U_(0xF) /**< \brief (DSU_MBCONTEXT) */ +#define DSU_MBCONTEXT_STEP_DOWN_R0W1 (DSU_MBCONTEXT_STEP_DOWN_R0W1_Val << DSU_MBCONTEXT_STEP_Pos) +#define DSU_MBCONTEXT_STEP_UP_R1W0R0W1 (DSU_MBCONTEXT_STEP_UP_R1W0R0W1_Val << DSU_MBCONTEXT_STEP_Pos) +#define DSU_MBCONTEXT_STEP_UP_R1W0 (DSU_MBCONTEXT_STEP_UP_R1W0_Val << DSU_MBCONTEXT_STEP_Pos) +#define DSU_MBCONTEXT_STEP_UP_R0W1R1W0 (DSU_MBCONTEXT_STEP_UP_R0W1R1W0_Val << DSU_MBCONTEXT_STEP_Pos) +#define DSU_MBCONTEXT_STEP_UP_R0 (DSU_MBCONTEXT_STEP_UP_R0_Val << DSU_MBCONTEXT_STEP_Pos) +#define DSU_MBCONTEXT_STEP_UP_R0R0W0R0W1 (DSU_MBCONTEXT_STEP_UP_R0R0W0R0W1_Val << DSU_MBCONTEXT_STEP_Pos) +#define DSU_MBCONTEXT_STEP_UP_R1R1W1R1W0 (DSU_MBCONTEXT_STEP_UP_R1R1W1R1W0_Val << DSU_MBCONTEXT_STEP_Pos) +#define DSU_MBCONTEXT_STEP_DOWN_R0R0W0R0W1 (DSU_MBCONTEXT_STEP_DOWN_R0R0W0R0W1_Val << DSU_MBCONTEXT_STEP_Pos) +#define DSU_MBCONTEXT_STEP_DOWN_R1R1W1R1W0 (DSU_MBCONTEXT_STEP_DOWN_R1R1W1R1W0_Val << DSU_MBCONTEXT_STEP_Pos) +#define DSU_MBCONTEXT_STEP_UP_R0R0 (DSU_MBCONTEXT_STEP_UP_R0R0_Val << DSU_MBCONTEXT_STEP_Pos) +#define DSU_MBCONTEXT_STEP_DOWN_R1W0R0W1 (DSU_MBCONTEXT_STEP_DOWN_R1W0R0W1_Val << DSU_MBCONTEXT_STEP_Pos) +#define DSU_MBCONTEXT_STEP_DOWN_R1R1 (DSU_MBCONTEXT_STEP_DOWN_R1R1_Val << DSU_MBCONTEXT_STEP_Pos) +#define DSU_MBCONTEXT_PORT_Pos 10 /**< \brief (DSU_MBCONTEXT) DPRAM Port Index */ +#define DSU_MBCONTEXT_PORT (_U_(0x1) << DSU_MBCONTEXT_PORT_Pos) +#define DSU_MBCONTEXT_MASK _U_(0x000007FF) /**< \brief (DSU_MBCONTEXT) MASK Register */ + +/* -------- DSU_MBENABLE0 : (DSU Offset: 0x0060) (R/W 32) MBIST Memory Enable 0 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ENABLE0:1; /*!< bit: 0 Memory 0 MBIST Enable */ + uint32_t ENABLE1:1; /*!< bit: 1 Memory 1 MBIST Enable */ + uint32_t ENABLE2:1; /*!< bit: 2 Memory 2 MBIST Enable */ + uint32_t ENABLE3:1; /*!< bit: 3 Memory 3 MBIST Enable */ + uint32_t ENABLE4:1; /*!< bit: 4 Memory 4 MBIST Enable */ + uint32_t ENABLE5:1; /*!< bit: 5 Memory 5 MBIST Enable */ + uint32_t ENABLE6:1; /*!< bit: 6 Memory 6 MBIST Enable */ + uint32_t ENABLE7:1; /*!< bit: 7 Memory 7 MBIST Enable */ + uint32_t ENABLE8:1; /*!< bit: 8 Memory 8 MBIST Enable */ + uint32_t ENABLE9:1; /*!< bit: 9 Memory 9 MBIST Enable */ + uint32_t ENABLE10:1; /*!< bit: 10 Memory 10 MBIST Enable */ + uint32_t ENABLE11:1; /*!< bit: 11 Memory 11 MBIST Enable */ + uint32_t ENABLE12:1; /*!< bit: 12 Memory 12 MBIST Enable */ + uint32_t ENABLE13:1; /*!< bit: 13 Memory 13 MBIST Enable */ + uint32_t ENABLE14:1; /*!< bit: 14 Memory 14 MBIST Enable */ + uint32_t ENABLE15:1; /*!< bit: 15 Memory 15 MBIST Enable */ + uint32_t ENABLE16:1; /*!< bit: 16 Memory 16 MBIST Enable */ + uint32_t ENABLE17:1; /*!< bit: 17 Memory 17 MBIST Enable */ + uint32_t ENABLE18:1; /*!< bit: 18 Memory 18 MBIST Enable */ + uint32_t ENABLE19:1; /*!< bit: 19 Memory 19 MBIST Enable */ + uint32_t ENABLE20:1; /*!< bit: 20 Memory 20 MBIST Enable */ + uint32_t ENABLE21:1; /*!< bit: 21 Memory 21 MBIST Enable */ + uint32_t ENABLE22:1; /*!< bit: 22 Memory 22 MBIST Enable */ + uint32_t ENABLE23:1; /*!< bit: 23 Memory 23 MBIST Enable */ + uint32_t ENABLE24:1; /*!< bit: 24 Memory 24 MBIST Enable */ + uint32_t ENABLE25:1; /*!< bit: 25 Memory 25 MBIST Enable */ + uint32_t ENABLE26:1; /*!< bit: 26 Memory 26 MBIST Enable */ + uint32_t ENABLE27:1; /*!< bit: 27 Memory 27 MBIST Enable */ + uint32_t ENABLE28:1; /*!< bit: 28 Memory 28 MBIST Enable */ + uint32_t :3; /*!< bit: 29..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t ENABLE:29; /*!< bit: 0..28 Memory x MBIST Enable */ + uint32_t :3; /*!< bit: 29..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} DSU_MBENABLE0_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DSU_MBENABLE0_OFFSET 0x0060 /**< \brief (DSU_MBENABLE0 offset) MBIST Memory Enable 0 */ +#define DSU_MBENABLE0_RESETVALUE _U_(0x00000000) /**< \brief (DSU_MBENABLE0 reset_value) MBIST Memory Enable 0 */ + +#define DSU_MBENABLE0_ENABLE0_Pos 0 /**< \brief (DSU_MBENABLE0) Memory 0 MBIST Enable */ +#define DSU_MBENABLE0_ENABLE0 (_U_(1) << DSU_MBENABLE0_ENABLE0_Pos) +#define DSU_MBENABLE0_ENABLE1_Pos 1 /**< \brief (DSU_MBENABLE0) Memory 1 MBIST Enable */ +#define DSU_MBENABLE0_ENABLE1 (_U_(1) << DSU_MBENABLE0_ENABLE1_Pos) +#define DSU_MBENABLE0_ENABLE2_Pos 2 /**< \brief (DSU_MBENABLE0) Memory 2 MBIST Enable */ +#define DSU_MBENABLE0_ENABLE2 (_U_(1) << DSU_MBENABLE0_ENABLE2_Pos) +#define DSU_MBENABLE0_ENABLE3_Pos 3 /**< \brief (DSU_MBENABLE0) Memory 3 MBIST Enable */ +#define DSU_MBENABLE0_ENABLE3 (_U_(1) << DSU_MBENABLE0_ENABLE3_Pos) +#define DSU_MBENABLE0_ENABLE4_Pos 4 /**< \brief (DSU_MBENABLE0) Memory 4 MBIST Enable */ +#define DSU_MBENABLE0_ENABLE4 (_U_(1) << DSU_MBENABLE0_ENABLE4_Pos) +#define DSU_MBENABLE0_ENABLE5_Pos 5 /**< \brief (DSU_MBENABLE0) Memory 5 MBIST Enable */ +#define DSU_MBENABLE0_ENABLE5 (_U_(1) << DSU_MBENABLE0_ENABLE5_Pos) +#define DSU_MBENABLE0_ENABLE6_Pos 6 /**< \brief (DSU_MBENABLE0) Memory 6 MBIST Enable */ +#define DSU_MBENABLE0_ENABLE6 (_U_(1) << DSU_MBENABLE0_ENABLE6_Pos) +#define DSU_MBENABLE0_ENABLE7_Pos 7 /**< \brief (DSU_MBENABLE0) Memory 7 MBIST Enable */ +#define DSU_MBENABLE0_ENABLE7 (_U_(1) << DSU_MBENABLE0_ENABLE7_Pos) +#define DSU_MBENABLE0_ENABLE8_Pos 8 /**< \brief (DSU_MBENABLE0) Memory 8 MBIST Enable */ +#define DSU_MBENABLE0_ENABLE8 (_U_(1) << DSU_MBENABLE0_ENABLE8_Pos) +#define DSU_MBENABLE0_ENABLE9_Pos 9 /**< \brief (DSU_MBENABLE0) Memory 9 MBIST Enable */ +#define DSU_MBENABLE0_ENABLE9 (_U_(1) << DSU_MBENABLE0_ENABLE9_Pos) +#define DSU_MBENABLE0_ENABLE10_Pos 10 /**< \brief (DSU_MBENABLE0) Memory 10 MBIST Enable */ +#define DSU_MBENABLE0_ENABLE10 (_U_(1) << DSU_MBENABLE0_ENABLE10_Pos) +#define DSU_MBENABLE0_ENABLE11_Pos 11 /**< \brief (DSU_MBENABLE0) Memory 11 MBIST Enabl |