summaryrefslogtreecommitdiffstats
path: root/tmk_core/protocol/arm_atsam/clks.c
blob: 84ed6d83af5784a42636fa9051042d754e56a106 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
/*
Copyright 2018 Massdrop Inc.

This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 2 of the License, or
(at your option) any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with this program.  If not, see <http://www.gnu.org/licenses/>.
*/

#include "arm_atsam_protocol.h"

#include <string.h>

volatile clk_t    system_clks;
volatile uint64_t ms_clk;
uint32_t          usec_delay_mult;
#define USEC_DELAY_LOOP_CYCLES 3  // Sum of instruction cycles in us delay loop

const uint32_t sercom_apbbase[] = {(uint32_t)SERCOM0, (uint32_t)SERCOM1, (uint32_t)SERCOM2, (uint32_t)SERCOM3, (uint32_t)SERCOM4, (uint32_t)SERCOM5};
const uint8_t  sercom_pchan[]   = {7, 8, 23, 24, 34, 35};

#define USE_DPLL_IND 0
#define USE_DPLL_DEF GCLK_SOURCE_DPLL0

void CLK_oscctrl_init(void) {
    Oscctrl *posctrl = OSCCTRL;
    Gclk *   pgclk   = GCLK;

    DBGC(DC_CLK_OSC_INIT_BEGIN);

    // default setup on por
    system_clks.freq_dfll    = FREQ_DFLL_DEFAULT;
    system_clks.freq_gclk[0] = system_clks.freq_dfll;

    // configure and startup 16MHz xosc0
    posctrl->XOSCCTRL[0].bit.ENABLE   = 0;
    posctrl->XOSCCTRL[0].bit.STARTUP  = 0xD;
    posctrl->XOSCCTRL[0].bit.ENALC    = 1;
    posctrl->XOSCCTRL[0].bit.IMULT    = 5;
    posctrl->XOSCCTRL[0].bit.IPTAT    = 3;
    posctrl->XOSCCTRL[0].bit.ONDEMAND = 0;
    posctrl->XOSCCTRL[0].bit.XTALEN   = 1;
    posctrl->XOSCCTRL[0].bit.ENABLE   = 1;
    while (posctrl->STATUS.bit.XOSCRDY0 == 0) {
        DBGC(DC_CLK_OSC_INIT_XOSC0_SYNC);
    }
    system_clks.freq_xosc0 = FREQ_XOSC0;

    // configure and startup DPLL
    posctrl->Dpll[USE_DPLL_IND].DPLLCTRLA.bit.ENABLE = 0;
    while (posctrl->Dpll[USE_DPLL_IND].DPLLSYNCBUSY.bit.ENABLE) {
        DBGC(DC_CLK_OSC_INIT_DPLL_SYNC_DISABLE);
    }
    posctrl->Dpll[USE_DPLL_IND].DPLLCTRLB.bit.REFCLK = 2;          // select XOSC0 (16MHz)
    posctrl->Dpll[USE_DPLL_IND].DPLLCTRLB.bit.DIV    = 7;          // 16 MHz / (2 * (7 + 1)) = 1 MHz
    posctrl->Dpll[USE_DPLL_IND].DPLLRATIO.bit.LDR    = PLL_RATIO;  // 1 MHz * (PLL_RATIO(47) + 1) = 48MHz
    while (posctrl->Dpll[USE_DPLL_IND].DPLLSYNCBUSY.bit.DPLLRATIO) {
        DBGC(DC_CLK_OSC_INIT_DPLL_SYNC_RATIO);
    }
    posctrl->Dpll[USE_DPLL_IND].DPLLCTRLA.bit.ONDEMAND = 0;
    posctrl->Dpll[USE_DPLL_IND].DPLLCTRLA.bit.ENABLE   = 1;
    while (posctrl->Dpll[USE_DPLL_IND].DPLLSYNCBUSY.bit.ENABLE) {
        DBGC(DC_CLK_OSC_INIT_DPLL_SYNC_ENABLE);
    }
    while (posctrl->Dpll[USE_DPLL_IND].DPLLSTATUS.bit.LOCK == 0) {
        DBGC(DC_CLK_OSC_INIT_DPLL_WAIT_LOCK);
    }
    while (posctrl->Dpll[USE_DPLL_IND].DPLLSTATUS.bit.CLKRDY == 0) {
        DBGC(DC_CLK_OSC_INIT_DPLL_WAIT_CLKRDY);
    }
    system_clks.freq_dpll[0] = (system_clks.freq_xosc0 / 2 / (posctrl->Dpll[USE_DPLL_IND].DPLLCTRLB.bit.DIV + 1)) * (posctrl->Dpll[USE_DPLL_IND].DPLLRATIO.bit.LDR + 1);

    // change gclk0 to DPLL
    pgclk->GENCTRL[GEN_DPLL0].bit.SRC = USE_DPLL_DEF;
    while (pgclk->SYNCBUSY.bit.GENCTRL0) {
        DBGC(DC_CLK_OSC_INIT_GCLK_SYNC_GENCTRL0);
    }

    system_clks.freq_gclk[0] = system_clks.freq_dpll[0];

    usec_delay_mult = system_clks.freq_gclk[0] / (USEC_DELAY_LOOP_CYCLES * 1000000);
    if (usec_delay_mult < 1) usec_delay_mult = 1;  // Never allow a multiplier of zero

    DBGC(DC_CLK_OSC_INIT_COMPLETE);
}

// configure for 1MHz (1 usec timebase)
// call CLK_set_gclk_freq(GEN_TC45, FREQ_TC45_DEFAULT);
uint32_t CLK_set_gclk_freq(uint8_t gclkn, uint32_t freq) {
    Gclk *pgclk = GCLK;

    DBGC(DC_CLK_SET_GCLK_FREQ_BEGIN);

    while (pgclk->SYNCBUSY.vec.GENCTRL) {
        DBGC(DC_CLK_SET_GCLK_FREQ_SYNC_1);
    }
    pgclk->GENCTRL[gclkn].bit.SRC = USE_DPLL_DEF;
    while (pgclk->SYNCBUSY.vec.GENCTRL) {
        DBGC(DC_CLK_SET_GCLK_FREQ_SYNC_2);
    }
    pgclk->GENCTRL[gclkn].bit.DIV = (uint8_t)(system_clks.freq_dpll[0] / freq);
    while (pgclk->SYNCBUSY.vec.GENCTRL) {
        DBGC(DC_CLK_SET_GCLK_FREQ_SYNC_3);
    }
    pgclk->GENCTRL[gclkn].bit.DIVSEL = 0;
    while (pgclk->SYNCBUSY.vec.GENCTRL) {
        DBGC(DC_CLK_SET_GCLK_FREQ_SYNC_4);
    }
    pgclk->GENCTRL[gclkn].bit.GENEN = 1;
    while (pgclk->SYNCBUSY.vec.GENCTRL) {
        DBGC(DC_CLK_SET_GCLK_FREQ_SYNC_5);
    }
    system_clks.freq_gclk[gclkn] = system_clks.freq_dpll[0] / pgclk->GENCTRL[gclkn].bit.DIV;

    DBGC(DC_CLK_SET_GCLK_FREQ_COMPLETE);

    return system_clks.freq_gclk[gclkn];
}

void CLK_init_osc(void) {
    uint8_t gclkn = GEN_OSC0;
    Gclk *  pgclk = GCLK;

    DBGC(DC_CLK_INIT_OSC_BEGIN);

    while (pgclk->SYNCBUSY.vec.GENCTRL) {
        DBGC(DC_CLK_INIT_OSC_SYNC_1);
    }
    pgclk->GENCTRL[gclkn].bit.SRC = GCLK_SOURCE_XOSC0;
    while (pgclk->SYNCBUSY.vec.GENCTRL) {
        DBGC(DC_CLK_INIT_OSC_SYNC_2);
    }
    pgclk->GENCTRL[gclkn].bit.DIV = 1;
    while (pgclk->SYNCBUSY.vec.GENCTRL) {
        DBGC(DC_CLK_INIT_OSC_SYNC_3);
    }
    pgclk->GENCTRL[gclkn].bit.DIVSEL = 0;
    while (pgclk->SYNCBUSY.vec.GENCTRL) {
        DBGC(DC_CLK_INIT_OSC_SYNC_4);
    }
    pgclk->GENCTRL[gclkn].bit.GENEN = 1;
    while (pgclk->SYNCBUSY.vec.GENCTRL) {
        DBGC(DC_CLK_INIT_OSC_SYNC_5);
    }
    system_clks.freq_gclk[gclkn] = system_clks.freq_xosc0;

    DBGC(DC_CLK_INIT_OSC_COMPLETE);
}

void CLK_reset_time(void) {
    Tc *ptc4 = TC4;
    Tc *ptc0 = TC0;

    ms_clk = 0;

    DBGC(DC_CLK_RESET_TIME_BEGIN);

    // stop counters
    ptc4->COUNT16.CTRLA.bit.ENABLE = 0;
    while (ptc4->COUNT16.SYNCBUSY.bit.ENABLE) {
    }
    ptc0->COUNT32.CTRLA.bit.ENABLE = 0;
    while (ptc0->COUNT32.SYNCBUSY.bit.ENABLE) {
    }
    // zero counters
    ptc4->COUNT16.COUNT.reg = 0;
    while (ptc4->COUNT16.SYNCBUSY.bit.COUNT) {
    }
    ptc0->COUNT32.COUNT.reg = 0;
    while (ptc0->COUNT32.SYNCBUSY.bit.COUNT) {
    }
    // start counters
    ptc0->COUNT32.CTRLA.bit.ENABLE = 1;
    while (ptc0->COUNT32.SYNCBUSY.bit.ENABLE) {
    }
    ptc4->COUNT16.CTRLA.bit.ENABLE = 1;
    while (ptc4->COUNT16.SYNCBUSY.bit.ENABLE) {
    }

    DBGC(DC_CLK_RESET_TIME_COMPLETE);
}

void TC4_Handler() {
    if (TC4->COUNT16.INTFLAG.bit.MC0) {
        TC4->COUNT16.INTFLAG.reg = TC_INTENCLR_MC0;
        ms_clk++;
    }
}

uint32_t CLK_enable_timebase(void) {
    Gclk * pgclk  = GCLK;
    Mclk * pmclk  = MCLK;
    Tc *   ptc4   = TC4;
    Tc *   ptc0   = TC0;
    Evsys *pevsys = EVSYS;

    DBGC(DC_CLK_ENABLE_TIMEBASE_BEGIN);

    // gclk2  highspeed time base
    CLK_set_gclk_freq(GEN_TC45, FREQ_TC45_DEFAULT);
    CLK_init_osc();

    // unmask TC4, sourcegclk2 to TC4
    pmclk->APBCMASK.bit.TC4_             = 1;
    pgclk->PCHCTRL[TC4_GCLK_ID].bit.GEN  = GEN_TC45;
    pgclk->PCHCTRL[TC4_GCLK_ID].bit.CHEN = 1;

    // configure TC4
    DBGC(DC_CLK_ENABLE_TIMEBASE_TC4_BEGIN);
    ptc4->COUNT16.CTRLA.bit.ENABLE = 0;
    while (ptc4->COUNT16.SYNCBUSY.bit.ENABLE) {
        DBGC(DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_DISABLE);
    }
    ptc4->COUNT16.CTRLA.bit.SWRST = 1;
    while (ptc4->COUNT16.SYNCBUSY.bit.SWRST) {
        DBGC(DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_SWRST_1);
    }
    while (ptc4->COUNT16.CTRLA.bit.SWRST) {
        DBGC(DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_SWRST_2);
    }

    // CTRLA defaults
    // CTRLB as default, counting up
    ptc4->COUNT16.CTRLBCLR.reg = 5;
    while (ptc4->COUNT16.SYNCBUSY.bit.CTRLB) {
        DBGC(DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_CLTRB);
    }
    ptc4->COUNT16.CC[0].reg = 999;
    while (ptc4->COUNT16.SYNCBUSY.bit.CC0) {
        DBGC(DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_CC0);
    }
    // ptc4->COUNT16.DBGCTRL.bit.DBGRUN = 1;

    // wave mode
    ptc4->COUNT16.WAVE.bit.WAVEGEN = 1;  // MFRQ match frequency mode, toggle each CC match
    // generate event for next stage
    ptc4->COUNT16.EVCTRL.bit.MCEO0 = 1;

    NVIC_EnableIRQ(TC4_IRQn);
    ptc4->COUNT16.INTENSET.bit.MC0 = 1;

    DBGC(DC_CLK_ENABLE_TIMEBASE_TC4_COMPLETE);

    // unmask TC0,1, sourcegclk2 to TC0,1
    pmclk->APBAMASK.bit.TC0_             = 1;
    pgclk->PCHCTRL[TC0_GCLK_ID].bit.GEN  = GEN_TC45;
    pgclk->PCHCTRL[TC0_GCLK_ID].bit.CHEN = 1;

    pmclk->APBAMASK.bit.TC1_             = 1;
    pgclk->PCHCTRL[TC1_GCLK_ID].bit.GEN  = GEN_TC45;
    pgclk->PCHCTRL[TC1_GCLK_ID].bit.CHEN = 1;

    // configure TC0
    DBGC(DC_CLK_ENABLE_TIMEBASE_TC0_BEGIN);
    ptc0->COUNT32.CTRLA.bit.ENABLE = 0;
    while (ptc0->COUNT32.SYNCBUSY.bit.ENABLE) {
        DBGC(DC_CLK_ENABLE_TIMEBASE_TC0_SYNC_DISABLE);
    }
    ptc0->COUNT32.CTRLA.bit.SWRST = 1;
    while (ptc0->COUNT32.SYNCBUSY.bit.SWRST) {
        DBGC(DC_CLK_ENABLE_TIMEBASE_TC0_SYNC_SWRST_1);
    }
    while (ptc0->COUNT32.CTRLA.bit.SWRST) {
        DBGC(DC_CLK_ENABLE_TIMEBASE_TC0_SYNC_SWRST_2);
    }
    // CTRLA as default
    ptc0->COUNT32.CTRLA.bit.MODE   = 2;  // 32 bit mode
    ptc0->COUNT32.EVCTRL.bit.TCEI  = 1;  // enable incoming events
    ptc0->COUNT32.EVCTRL.bit.EVACT = 2;  // count events

    DBGC(DC_CLK_ENABLE_TIMEBASE_TC0_COMPLETE);

    DBGC(DC_CLK_ENABLE_TIMEBASE_EVSYS_BEGIN);

    // configure event system
    pmclk->APBBMASK.bit.EVSYS_               = 1;
    pgclk->PCHCTRL[EVSYS_GCLK_ID_0].bit.GEN  = GEN_TC45;
    pgclk->PCHCTRL[EVSYS_GCLK_ID_0].bit.CHEN = 1;
    pevsys->USER[44].reg                     = EVSYS_ID_USER_PORT_EV_0;               // TC0 will get event channel 0
    pevsys->Channel[0].CHANNEL.bit.EDGSEL    = EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val;  // Rising edge
    pevsys->Channel[0].CHANNEL.bit.PATH      = EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val;    // Synchronous
    pevsys->Channel[0].CHANNEL.bit.EVGEN     = EVSYS_ID_GEN_TC4_MCX_0;                // TC4 MC0

    DBGC(DC_CLK_ENABLE_TIMEBASE_EVSYS_COMPLETE);

    CLK_reset_time();

    ADC0_clock_init();

    DBGC(DC_CLK_ENABLE_TIMEBASE_COMPLETE);

    return 0;
}

void CLK_delay_us(uint32_t usec) {
    asm("CBZ R0, return\n\t"  // If usec == 0, branch to return label
    );
    asm("MULS R0, %0\n\t"        // Multiply R0(usec) by usec_delay_mult and store in R0
        ".balign 16\n\t"         // Ensure loop is aligned for fastest performance
        "loop: SUBS R0, #1\n\t"  // Subtract 1 from R0 and update flags (1 cycle)
        "BNE loop\n\t"           // Branch if non-zero to loop label (2 cycles)  NOTE: USEC_DELAY_LOOP_CYCLES is the sum of loop cycles
        "return:\n\t"            // Return label
        :                        // No output registers
        : "r"(usec_delay_mult)   // For %0
    );
    // Note: BX LR generated
}

void CLK_delay_ms(uint64_t msec) {
    msec += timer_read64();
    while (msec > timer_read64()) {
    }
}

void clk_enable_sercom_apbmask(int sercomn) {
    Mclk *pmclk = MCLK;
    switch (sercomn) {
        case 0:
            pmclk->APBAMASK.bit.SERCOM0_ = 1;
            break;
        case 1:
            pmclk->APBAMASK.bit.SERCOM1_ = 1;
            break;
        case 2:
            pmclk->APBBMASK.bit.SERCOM2_ = 1;
            break;
        case 3:
            pmclk->APBBMASK.bit.SERCOM3_ = 1;
            break;
        default:
            break;
    }
}

// call CLK_oscctrl_init first
// call CLK_set_spi_freq(CHAN_SERCOM_SPI, FREQ_SPI_DEFAULT);
uint32_t CLK_set_spi_freq(uint8_t sercomn, uint32_t freq) {
    DBGC(DC_CLK_SET_SPI_FREQ_BEGIN);

    Gclk *  pgclk   = GCLK;
    Sercom *psercom = (Sercom *)sercom_apbbase[sercomn];
    clk_enable_sercom_apbmask(sercomn);

    // all gclk0 for now
    pgclk->PCHCTRL[sercom_pchan[sercomn]].bit.GEN  = 0;
    pgclk->PCHCTRL[sercom_pchan[sercomn]].bit.CHEN = 1;

    psercom->I2CM.CTRLA.bit.SWRST = 1;
    while (psercom->I2CM.SYNCBUSY.bit.SWRST) {
    }
    while (psercom->I2CM.CTRLA.bit.SWRST) {
    }

    psercom->SPI.BAUD.reg            = (uint8_t)(system_clks.freq_gclk[0] / 2 / freq - 1);
    system_clks.freq_spi             = system_clks.freq_gclk[0] / 2 / (psercom->SPI.BAUD.reg + 1);
    system_clks.freq_sercom[sercomn] = system_clks.freq_spi;

    DBGC(DC_CLK_SET_SPI_FREQ_COMPLETE);

    return system_clks.freq_spi;
}

// call CLK_oscctrl_init first
// call CLK_set_i2c0_freq(CHAN_SERCOM_I2C0, FREQ_I2C0_DEFAULT);
uint32_t CLK_set_i2c0_freq(uint8_t sercomn, uint32_t freq) {
    DBGC(DC_CLK_SET_I2C0_FREQ_BEGIN);

    Gclk *  pgclk   = GCLK;
    Sercom *psercom = (Sercom *)sercom_apbbase[sercomn];
    clk_enable_sercom_apbmask(sercomn);

    // all gclk0 for now
    pgclk->PCHCTRL[sercom_pchan[sercomn]].bit.GEN  = 0;
    pgclk->PCHCTRL[sercom_pchan[sercomn]].bit.CHEN = 1;

    psercom->I2CM.CTRLA.bit.SWRST = 1;
    while (psercom->I2CM.SYNCBUSY.bit.SWRST) {
    }
    while (psercom->I2CM.CTRLA.bit.SWRST) {
    }

    psercom->I2CM.BAUD.bit.BAUD      = (uint8_t)(system_clks.freq_gclk[0] / 2 / freq - 1);
    system_clks.freq_i2c0            = system_clks.freq_gclk[0] / 2 / (psercom->I2CM.BAUD.bit.BAUD + 1);
    system_clks.freq_sercom[sercomn] = system_clks.freq_i2c0;

    DBGC(DC_CLK_SET_I2C0_FREQ_COMPLETE);

    return system_clks.freq_i2c0;
}

// call CLK_oscctrl_init first
// call CLK_set_i2c1_freq(CHAN_SERCOM_I2C1, FREQ_I2C1_DEFAULT);
uint32_t CLK_set_i2c1_freq(uint8_t sercomn, uint32_t freq) {
    DBGC(DC_CLK_SET_I2C1_FREQ_BEGIN);

    Gclk *  pgclk   = GCLK;
    Sercom *psercom = (Sercom *)sercom_apbbase[sercomn];
    clk_enable_sercom_apbmask(sercomn);

    // all gclk0 for now
    pgclk->PCHCTRL[sercom_pchan[sercomn]].bit.GEN  = 0;
    pgclk->PCHCTRL[sercom_pchan[sercomn]].bit.CHEN = 1;

    psercom->I2CM.CTRLA.bit.SWRST = 1;
    while (psercom->I2CM.SYNCBUSY.bit.SWRST) {
    }
    while (psercom->I2CM.CTRLA.bit.SWRST) {
    }

    psercom->I2CM.BAUD.bit.BAUD      = (uint8_t)(system_clks.freq_gclk[0] / 2 / freq - 10);
    system_clks.freq_i2c1            = system_clks.freq_gclk[0] / 2 / (psercom->I2CM.BAUD.bit.BAUD + 10);
    system_clks.freq_sercom[sercomn] = system_clks.freq_i2c1;

    DBGC(DC_CLK_SET_I2C1_FREQ_COMPLETE);

    return system_clks.freq_i2c1;
}

void CLK_init(void) {
    DBGC(DC_CLK_INIT_BEGIN);

    memset((void *)&system_clks, 0, sizeof(system_clks));

    CLK_oscctrl_init();
    CLK_enable_timebase();

    DBGC(DC_CLK_INIT_COMPLETE);
}