summaryrefslogtreecommitdiffstats
path: root/platforms/chibios/drivers/eeprom/eeprom_teensy.c
blob: c8777febde3a5c0c1751549ecd3da771af519553 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
#include <ch.h>
#include <hal.h>

#include "eeprom_teensy.h"
#include "eeconfig.h"

/*************************************/
/*          Hardware backend         */
/*                                   */
/*    Code from PJRC/Teensyduino     */
/*************************************/

/* Teensyduino Core Library
 * http://www.pjrc.com/teensy/
 * Copyright (c) 2013 PJRC.COM, LLC.
 *
 * Permission is hereby granted, free of charge, to any person obtaining
 * a copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sublicense, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * 1. The above copyright notice and this permission notice shall be
 * included in all copies or substantial portions of the Software.
 *
 * 2. If the Software is incorporated into a build system that allows
 * selection among a list of target devices, then similar target
 * devices manufactured by PJRC.COM must be included in the list of
 * target devices and selectable in the same manner.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#if defined(K20x) /* chip selection */
/* Teensy 3.0, 3.1, 3.2; mchck; infinity keyboard */

/*
    ^^^ Here be dragons:
        NXP AppNote AN4282 section 3.1 states that partitioning must only be done once.
        Once EEPROM partitioning is done, the size is locked to this initial configuration.
        Attempts to modify the EEPROM_SIZE setting may brick your board.
*/

// Writing unaligned 16 or 32 bit data is handled automatically when
// this is defined, but at a cost of extra code size.  Without this,
// any unaligned write will cause a hard fault exception!  If you're
// absolutely sure all 16 and 32 bit writes will be aligned, you can
// remove the extra unnecessary code.
//
#    define HANDLE_UNALIGNED_WRITES

// Minimum EEPROM Endurance
// ------------------------
#    if (EEPROM_SIZE == 2048) // 35000 writes/byte or 70000 writes/word
#        define EEESIZE 0x33
#    elif (EEPROM_SIZE == 1024) // 75000 writes/byte or 150000 writes/word
#        define EEESIZE 0x34
#    elif (EEPROM_SIZE == 512) // 155000 writes/byte or 310000 writes/word
#        define EEESIZE 0x35
#    elif (EEPROM_SIZE == 256) // 315000 writes/byte or 630000 writes/word
#        define EEESIZE 0x36
#    elif (EEPROM_SIZE == 128) // 635000 writes/byte or 1270000 writes/word
#        define EEESIZE 0x37
#    elif (EEPROM_SIZE == 64) // 1275000 writes/byte or 2550000 writes/word
#        define EEESIZE 0x38
#    elif (EEPROM_SIZE == 32) // 2555000 writes/byte or 5110000 writes/word
#        define EEESIZE 0x39
#    endif

/** \brief eeprom initialization
 *
 * FIXME: needs doc
 */
void eeprom_initialize(void) {
    uint32_t count          = 0;
    uint16_t do_flash_cmd[] = {0xf06f, 0x037f, 0x7003, 0x7803, 0xf013, 0x0f80, 0xd0fb, 0x4770};
    uint8_t  status;

    if (FTFL->FCNFG & FTFL_FCNFG_RAMRDY) {
        // FlexRAM is configured as traditional RAM
        // We need to reconfigure for EEPROM usage
        FTFL->FCCOB0 = 0x80;    // PGMPART = Program Partition Command
        FTFL->FCCOB4 = EEESIZE; // EEPROM Size
        FTFL->FCCOB5 = 0x03;    // 0K for Dataflash, 32K for EEPROM backup
        __disable_irq();
        // do_flash_cmd() must execute from RAM.  Luckily the C syntax is simple...
        (*((void (*)(volatile uint8_t *))((uint32_t)do_flash_cmd | 1)))(&(FTFL->FSTAT));
        __enable_irq();
        status = FTFL->FSTAT;
        if (status & (FTFL_FSTAT_RDCOLERR | FTFL_FSTAT_ACCERR | FTFL_FSTAT_FPVIOL)) {
            FTFL->FSTAT = (status & (FTFL_FSTAT_RDCOLERR | FTFL_FSTAT_ACCERR | FTFL_FSTAT_FPVIOL));
            return; // error
        }
    }
    // wait for eeprom to become ready (is this really necessary?)
    while (!(FTFL->FCNFG & FTFL_FCNFG_EEERDY)) {
        if (++count > 20000) break;
    }
}

#    define FlexRAM ((uint8_t *)0x14000000)

/** \brief eeprom read byte
 *
 * FIXME: needs doc
 */
uint8_t eeprom_read_byte(const uint8_t *addr) {
    uint32_t offset = (uint32_t)addr;
    if (offset >= EEPROM_SIZE) return 0;
    if (!(FTFL->FCNFG & FTFL_FCNFG_EEERDY)) eeprom_initialize();
    return FlexRAM[offset];
}

/** \brief eeprom read word
 *
 * FIXME: needs doc
 */
uint16_t eeprom_read_word(const uint16_t *addr) {
    uint32_t offset = (uint32_t)addr;
    if (offset >= EEPROM_SIZE - 1) return 0;
    if (!(FTFL->FCNFG & FTFL_FCNFG_EEERDY)) eeprom_initialize();
    return *(uint16_t *)(&FlexRAM[offset]);
}

/** \brief eeprom read dword
 *
 * FIXME: needs doc
 */
uint32_t eeprom_read_dword(const uint32_t *addr) {
    uint32_t offset = (uint32_t)addr;
    if (offset >= EEPROM_SIZE - 3) return 0;
    if (!(FTFL->FCNFG & FTFL_FCNFG_EEERDY)) eeprom_initialize();
    return *(uint32_t *)(&FlexRAM[offset]);
}

/** \brief eeprom read block
 *
 * FIXME: needs doc
 */
void eeprom_read_block(void *buf, const void *addr, uint32_t len) {
    uint32_t offset = (uint32_t)addr;
    uint8_t *dest   = (uint8_t *)buf;
    uint32_t end    = offset + len;

    if (!(FTFL->FCNFG & FTFL_FCNFG_EEERDY)) eeprom_initialize();
    if (end > EEPROM_SIZE) end = EEPROM_SIZE;
    while (offset < end) {
        *dest++ = FlexRAM[offset++];
    }
}

/** \brief eeprom is ready
 *
 * FIXME: needs doc
 */
int eeprom_is_ready(void) {
    return (FTFL->FCNFG & FTFL_FCNFG_EEERDY) ? 1 : 0;
}

/** \brief flexram wait
 *
 * FIXME: needs doc
 */
static void flexram_wait(void) {
    while (!(FTFL->FCNFG & FTFL_FCNFG_EEERDY)) {
        // TODO: timeout
    }
}

/** \brief eeprom_write_byte
 *
 * FIXME: needs doc
 */
void eeprom_write_byte(uint8_t *addr, uint8_t value) {
    uint32_t offset = (uint32_t)addr;

    if (offset >= EEPROM_SIZE) return;
    if (!(FTFL->FCNFG & FTFL_FCNFG_EEERDY)) eeprom_initialize();
    if (FlexRAM[offset] != value) {
        FlexRAM[offset] = value;
        flexram_wait();
    }
}

/** \brief eeprom write word
 *
 * FIXME: needs doc
 */
void eeprom_write_word(uint16_t *addr, uint16_t value) {
    uint32_t offset = (uint32_t)addr;

    if (offset >= EEPROM_SIZE - 1) return;
    if (!(FTFL->FCNFG & FTFL_FCNFG_EEERDY)) eeprom_initialize();
#    ifdef HANDLE_UNALIGNED_WRITES
    if ((offset & 1) == 0) {
#    endif
        if (*(uint16_t *)(&FlexRAM[offset]) != value) {
            *(uint16_t *)(&FlexRAM[offset]) = value;
            flexram_wait();
        }
#    ifdef HANDLE_UNALIGNED_WRITES
    } else {
        if (FlexRAM[offset] != value) {
            FlexRAM[offset] = value;
            flexram_wait();
        }
        if (FlexRAM[offset + 1] != (value >> 8)) {
            FlexRAM[offset + 1] = value >> 8;
            flexram_wait();
        }
    }
#    endif
}

/** \brief eeprom write dword
 *
 * FIXME: needs doc
 */
void eeprom_write_dword(uint32_t *addr, uint32_t value) {
    uint32_t offset = (uint32_t)addr;

    if (offset >= EEPROM_SIZE - 3) return;
    if (!(FTFL->FCNFG & FTFL_FCNFG_EEERDY)) eeprom_initialize();
#    ifdef HANDLE_UNALIGNED_WRITES
    switch (offset & 3) {
        case 0:
#    endif
            if (*(uint32_t *)(&FlexRAM[offset]) != value) {
                *(uint32_t *)(&FlexRAM[offset]) = value;
                flexram_wait();
            }
            return;
#    ifdef HANDLE_UNALIGNED_WRITES
        case 2:
            if (*(uint16_t *)(&FlexRAM[offset]) != value) {
                *(uint16_t *)(&FlexRAM[offset]) = value;
                flexram_wait();
            }
            if (*(uint16_t *)(&FlexRAM[offset + 2]) != (value >> 16)) {
                *(uint16_t *)(&FlexRAM[offset + 2]) = value >> 16;
                flexram_wait();
            }
            return;
        default:
            if (FlexRAM[offset] != value) {
                FlexRAM[offset] = value;
                flexram_wait();
            }
            if (*(uint16_t *)(&FlexRAM[offset + 1]) != (value >> 8)) {
                *(uint16_t *)(&FlexRAM[offset + 1]) = value >> 8;
                flexram_wait();
            }
            if (FlexRAM[offset + 3] != (value >> 24)) {
                FlexRAM[offset + 3] = value >> 24;
                flexram_wait();
            }
    }
#    endif
}

/** \brief eeprom write block
 *
 * FIXME: needs doc
 */
void eeprom_write_block(const void *buf, void *addr, uint32_t len) {
    uint32_t       offset = (uint32_t)addr;
    const uint8_t *src    = (const uint8_t *)buf;

    if (offset >= EEPROM_SIZE) return;
    if (!(FTFL->FCNFG & FTFL_FCNFG_EEERDY)) eeprom_initialize();
    if (len >= EEPROM_SIZE) len = EEPROM_SIZE;
    if (offset + len >= EEPROM_SIZE) len = EEPROM_SIZE - offset;
    while (len > 0) {
        uint32_t lsb = offset & 3;
        if (lsb == 0 && len >= 4) {
            // write aligned 32 bits
            uint32_t val32;
            val32 = *src++;
            val32 |= (*src++ << 8);
            val32 |= (*src++ << 16);
            val32 |= (*src++ << 24);
            if (*(uint32_t *)(&FlexRAM[offset]) != val32) {
                *(uint32_t *)(&FlexRAM[offset]) = val32;
                flexram_wait();
            }
            offset += 4;
            len -= 4;
        } else if ((lsb == 0 || lsb == 2) && len >= 2) {
            // write aligned 16 bits
            uint16_t val16;
            val16 = *src++;
            val16 |= (*src++ << 8);
            if (*(uint16_t *)(&FlexRAM[offset]) != val16) {
                *(uint16_t *)(&FlexRAM[offset]) = val16;
                flexram_wait();
            }
            offset += 2;
            len -= 2;
        } else {
            // write 8 bits
            uint8_t val8 = *src++;
            if (FlexRAM[offset] != val8) {
                FlexRAM[offset] = val8;
                flexram_wait();
            }
            offset++;
            len--;
        }
    }
}

/*
void do_flash_cmd(volatile uint8_t *fstat)
{
    *fstat = 0x80;
    while ((*fstat & 0x80) == 0) ; // wait
}
00000000 <do_flash_cmd>:
   0:	f06f 037f 	mvn.w	r3, #127	; 0x7f
   4:	7003      	strb	r3, [r0, #0]
   6:	7803      	ldrb	r3, [r0, #0]
   8:	f013 0f80 	tst.w	r3, #128	; 0x80
   c:	d0fb      	beq.n	6 <do_flash_cmd+0x6>
   e:	4770      	bx	lr
*/

#elif defined(KL2x) /* chip selection */
/* Teensy LC (emulated) */

#    define SYMVAL(sym) (uint32_t)(((uint8_t *)&(sym)) - ((uint8_t *)0))

extern uint32_t __eeprom_workarea_start__;
extern uint32_t __eeprom_workarea_end__;

static uint32_t flashend = 0;

void eeprom_initialize(void) {
    const uint16_t *p = (uint16_t *)SYMVAL(__eeprom_workarea_start__);

    do {
        if (*p++ == 0xFFFF) {
            flashend = (uint32_t)(p - 2);
            return;
        }
    } while (p < (uint16_t *)SYMVAL(__eeprom_workarea_end__));
    flashend = (uint32_t)(p - 1);
}

uint8_t eeprom_read_byte(const uint8_t *addr) {
    uint32_t        offset = (uint32_t)addr;
    const uint16_t *p      = (uint16_t *)SYMVAL(__eeprom_workarea_start__);
    const uint16_t *end    = (const uint16_t *)((uint32_t)flashend);
    uint16_t        val;
    uint8_t         data = 0xFF;

    if (!end) {
        eeprom_initialize();
        end = (const uint16_t *)((uint32_t)flashend);
    }
    if (offset < EEPROM_SIZE) {
        while (p <= end) {
            val = *p++;
            if ((val & 255) == offset) data = val >> 8;
        }
    }
    return data;
}

static void flash_write(const uint16_t *code, uint32_t addr, uint32_t data) {
    // with great power comes great responsibility....
    uint32_t stat;
    *(uint32_t *)&(FTFA->FCCOB3) = 0x06000000 | (addr & 0x00FFFFFC);
    *(uint32_t *)&(FTFA->FCCOB7) = data;
    __disable_irq();
    (*((void (*)(volatile uint8_t *))((uint32_t)code | 1)))(&(FTFA->FSTAT));
    __enable_irq();
    stat = FTFA->FSTAT & (FTFA_FSTAT_RDCOLERR | FTFA_FSTAT_ACCERR | FTFA_FSTAT_FPVIOL);
    if (stat) {
        FTFA->FSTAT = stat;
    }
    MCM->PLACR |= MCM_PLACR_CFCC;
}

void eeprom_write_byte(uint8_t *addr, uint8_t data) {
    uint32_t        offset = (uint32_t)addr;
    const uint16_t *p, *end = (const uint16_t *)((uint32_t)flashend);
    uint32_t        i, val, flashaddr;
    uint16_t        do_flash_cmd[] = {0x2380, 0x7003, 0x7803, 0xb25b, 0x2b00, 0xdafb, 0x4770};
    uint8_t         buf[EEPROM_SIZE];

    if (offset >= EEPROM_SIZE) return;
    if (!end) {
        eeprom_initialize();
        end = (const uint16_t *)((uint32_t)flashend);
    }
    if (++end < (uint16_t *)SYMVAL(__eeprom_workarea_end__)) {
        val       = (data << 8) | offset;
        flashaddr = (uint32_t)end;
        flashend  = flashaddr;
        if ((flashaddr & 2) == 0) {
            val |= 0xFFFF0000;
        } else {
            val <<= 16;
            val |= 0x0000FFFF;
        }
        flash_write(do_flash_cmd, flashaddr, val);
    } else {
        for (i = 0; i < EEPROM_SIZE; i++) {
            buf[i] = 0xFF;
        }
        val = 0;
        for (p = (uint16_t *)SYMVAL(__eeprom_workarea_start__); p < (uint16_t *)SYMVAL(__eeprom_workarea_end__); p++) {
            val = *p;
            if ((val & 255) < EEPROM_SIZE) {
                buf[val & 255] = val >> 8;
            }
        }
        buf[offset] = data;
        for (flashaddr = (uint32_t)(uint16_t *)SYMVAL(__eeprom_workarea_start__); flashaddr < (uint32_t)(uint16_t *)SYMVAL(__eeprom_workarea_end__); flashaddr += 1024) {
            *(uint32_t *)&(FTFA->FCCOB3) = 0x09000000 | flashaddr;
            __disable_irq();
            (*((void (*)(volatile uint8_t *))((uint32_t)do_flash_cmd | 1)))(&(FTFA->FSTAT));
            __enable_irq();
            val = FTFA->FSTAT & (FTFA_FSTAT_RDCOLERR | FTFA_FSTAT_ACCERR | FTFA_FSTAT_FPVIOL);
            ;
            if (val) FTFA->FSTAT = val;
            MCM->PLACR |= MCM_PLACR_CFCC;
        }
        flashaddr = (uint32_t)(uint16_t *)SYMVAL(__eeprom_workarea_start__);
        for (i = 0; i < EEPROM_SIZE; i++) {
            if (buf[i] == 0xFF) continue;
            if ((flashaddr & 2) == 0) {
                val = (buf[i] << 8) | i;
            } else {
                val = val | (buf[i] << 24) | (i << 16);
                flash_write(do_flash_cmd, flashaddr, val);
            }
            flashaddr += 2;
        }
        flashend = flashaddr;
        if ((flashaddr & 2)) {
            val |= 0xFFFF0000;
            flash_write(do_flash_cmd, flashaddr, val);
        }
    }
}

/*
void do_flash_cmd(volatile uint8_t *fstat)
{
        *fstat = 0x80;
        while ((*fstat & 0x80) == 0) ; // wait
}
00000000 <do_flash_cmd>:
   0:	2380      	movs	r3, #128	; 0x80
   2:	7003      	strb	r3, [r0, #0]
   4:	7803      	ldrb	r3, [r0, #0]
   6:	b25b      	sxtb	r3, r3
   8:	2b00      	cmp	r3, #0
   a:	dafb      	bge.n	4 <do_flash_cmd+0x4>
   c:	4770      	bx	lr
*/

uint16_t eeprom_read_word(const uint16_t *addr) {
    const uint8_t *p = (const uint8_t *)addr;
    return eeprom_read_byte(p) | (eeprom_read_byte(p + 1) << 8);
}

uint32_t eeprom_read_dword(const uint32_t *addr) {
    const uint8_t *p = (const uint8_t *)addr;
    return eeprom_read_byte(p) | (eeprom_read_byte(p + 1) << 8) | (eeprom_read_byte(p + 2) << 16) | (eeprom_read_byte(p + 3) << 24);
}

void eeprom_read_block(void *buf, const void *addr, uint32_t len) {
    const uint8_t *p    = (const uint8_t *)addr;
    uint8_t *      dest = (uint8_t *)buf;
    while (len--) {
        *dest++ = eeprom_read_byte(p++);
    }
}

int eeprom_is_ready(void) {
    return 1;
}

void eeprom_write_word(uint16_t *addr, uint16_t value) {
    uint8_t *p = (uint8_t *)addr;
    eeprom_write_byte(p++, value);
    eeprom_write_byte(p, value >> 8);
}

void eeprom_write_dword(uint32_t *addr, uint32_t value) {
    uint8_t *p = (uint8_t *)addr;
    eeprom_write_byte(p++, value);
    eeprom_write_byte(p++, value >> 8);
    eeprom_write_byte(p++, value >> 16);
    eeprom_write_byte(p, value >> 24);
}

void eeprom_write_block(const void *buf, void *addr, uint32_t len) {
    uint8_t *      p   = (uint8_t *)addr;
    const uint8_t *src = (const uint8_t *)buf;
    while (len--) {
        eeprom_write_byte(p++, *src++);
    }
}

#else
#    error Unsupported Teensy EEPROM.
#endif /* chip selection */
// The update functions just calls write for now, but could probably be optimized

void eeprom_update_byte(uint8_t *addr, uint8_t value) {
    eeprom_write_byte(addr, value);
}

void eeprom_update_word(uint16_t *addr, uint16_t value) {
    uint8_t *p = (uint8_t *)addr;
    eeprom_write_byte(p++, value);
    eeprom_write_byte(p, value >> 8);
}

void eeprom_update_dword(uint32_t *addr, uint32_t value) {
    uint8_t *p = (uint8_t *)addr;
    eeprom_write_byte(p++, value);
    eeprom_write_byte(p++, value >> 8);
    eeprom_write_byte(p++, value >> 16);
    eeprom_write_byte(p, value >> 24);
}

void eeprom_update_block(const void *buf, void *addr, size_t len) {
    uint8_t *      p   = (uint8_t *)addr;
    const uint8_t *src = (const uint8_t *)buf;
    while (len--) {
        eeprom_write_byte(p++, *src++);
    }
}