diff options
Diffstat (limited to 'tmk_core/protocol')
72 files changed, 1507 insertions, 1186 deletions
diff --git a/tmk_core/protocol/arm_atsam/adc.c b/tmk_core/protocol/arm_atsam/adc.c index 1ef1b11d57..3afcbddf10 100644 --- a/tmk_core/protocol/arm_atsam/adc.c +++ b/tmk_core/protocol/arm_atsam/adc.c @@ -27,10 +27,10 @@ uint16_t v_con_2_boot; void ADC0_clock_init(void) { DBGC(DC_ADC0_CLOCK_INIT_BEGIN); - MCLK->APBDMASK.bit.ADC0_ = 1; // ADC0 Clock Enable + MCLK->APBDMASK.bit.ADC0_ = 1; // ADC0 Clock Enable - GCLK->PCHCTRL[ADC0_GCLK_ID].bit.GEN = GEN_OSC0; // Select generator clock - GCLK->PCHCTRL[ADC0_GCLK_ID].bit.CHEN = 1; // Enable peripheral clock + GCLK->PCHCTRL[ADC0_GCLK_ID].bit.GEN = GEN_OSC0; // Select generator clock + GCLK->PCHCTRL[ADC0_GCLK_ID].bit.CHEN = 1; // Enable peripheral clock DBGC(DC_ADC0_CLOCK_INIT_COMPLETE); } @@ -39,15 +39,15 @@ void ADC0_init(void) { DBGC(DC_ADC0_INIT_BEGIN); // MCU - PORT->Group[1].DIRCLR.reg = 1 << 0; // PB00 as input 5V - PORT->Group[1].DIRCLR.reg = 1 << 1; // PB01 as input CON2 - PORT->Group[1].DIRCLR.reg = 1 << 2; // PB02 as input CON1 - PORT->Group[1].PMUX[0].bit.PMUXE = 1; // PB00 mux select B ADC 5V - PORT->Group[1].PMUX[0].bit.PMUXO = 1; // PB01 mux select B ADC CON2 - PORT->Group[1].PMUX[1].bit.PMUXE = 1; // PB02 mux select B ADC CON1 - PORT->Group[1].PINCFG[0].bit.PMUXEN = 1; // PB01 mux ADC Enable 5V - PORT->Group[1].PINCFG[1].bit.PMUXEN = 1; // PB01 mux ADC Enable CON2 - PORT->Group[1].PINCFG[2].bit.PMUXEN = 1; // PB02 mux ADC Enable CON1 + PORT->Group[1].DIRCLR.reg = 1 << 0; // PB00 as input 5V + PORT->Group[1].DIRCLR.reg = 1 << 1; // PB01 as input CON2 + PORT->Group[1].DIRCLR.reg = 1 << 2; // PB02 as input CON1 + PORT->Group[1].PMUX[0].bit.PMUXE = 1; // PB00 mux select B ADC 5V + PORT->Group[1].PMUX[0].bit.PMUXO = 1; // PB01 mux select B ADC CON2 + PORT->Group[1].PMUX[1].bit.PMUXE = 1; // PB02 mux select B ADC CON1 + PORT->Group[1].PINCFG[0].bit.PMUXEN = 1; // PB01 mux ADC Enable 5V + PORT->Group[1].PINCFG[1].bit.PMUXEN = 1; // PB01 mux ADC Enable CON2 + PORT->Group[1].PINCFG[2].bit.PMUXEN = 1; // PB02 mux ADC Enable CON1 // ADC ADC0->CTRLA.bit.SWRST = 1; @@ -81,7 +81,7 @@ void ADC0_init(void) { } // Settling - ADC0->SAMPCTRL.bit.SAMPLEN = 45; // Sampling Time Length: 1-63, 1 ADC CLK per + ADC0->SAMPCTRL.bit.SAMPLEN = 45; // Sampling Time Length: 1-63, 1 ADC CLK per while (ADC0->SYNCBUSY.bit.SAMPCTRL) { DBGC(DC_ADC0_SAMPCTRL_SYNCING_1); } diff --git a/tmk_core/protocol/arm_atsam/adc.h b/tmk_core/protocol/arm_atsam/adc.h index 9ab653e5a2..74fbb0e66f 100644 --- a/tmk_core/protocol/arm_atsam/adc.h +++ b/tmk_core/protocol/arm_atsam/adc.h @@ -34,4 +34,4 @@ extern uint16_t v_con_2_boot; void ADC0_clock_init(void); void ADC0_init(void); -#endif //_ADC_H_ +#endif //_ADC_H_ diff --git a/tmk_core/protocol/arm_atsam/arm_atsam_protocol.h b/tmk_core/protocol/arm_atsam/arm_atsam_protocol.h index 319ff8487d..db9827f6a2 100644 --- a/tmk_core/protocol/arm_atsam/arm_atsam_protocol.h +++ b/tmk_core/protocol/arm_atsam/arm_atsam_protocol.h @@ -42,6 +42,6 @@ along with this program. If not, see <http://www.gnu.org/licenses/>. # include "./usb/udc.h" # include "./usb/udi_cdc.h" -#endif // MD_BOOTLOADER +#endif // MD_BOOTLOADER -#endif //_ARM_ATSAM_PROTOCOL_H_ +#endif //_ARM_ATSAM_PROTOCOL_H_ diff --git a/tmk_core/protocol/arm_atsam/clks.c b/tmk_core/protocol/arm_atsam/clks.c index 84ed6d83af..9b9475c616 100644 --- a/tmk_core/protocol/arm_atsam/clks.c +++ b/tmk_core/protocol/arm_atsam/clks.c @@ -22,7 +22,7 @@ along with this program. If not, see <http://www.gnu.org/licenses/>. volatile clk_t system_clks; volatile uint64_t ms_clk; uint32_t usec_delay_mult; -#define USEC_DELAY_LOOP_CYCLES 3 // Sum of instruction cycles in us delay loop +#define USEC_DELAY_LOOP_CYCLES 3 // Sum of instruction cycles in us delay loop const uint32_t sercom_apbbase[] = {(uint32_t)SERCOM0, (uint32_t)SERCOM1, (uint32_t)SERCOM2, (uint32_t)SERCOM3, (uint32_t)SERCOM4, (uint32_t)SERCOM5}; const uint8_t sercom_pchan[] = {7, 8, 23, 24, 34, 35}; @@ -59,9 +59,9 @@ void CLK_oscctrl_init(void) { while (posctrl->Dpll[USE_DPLL_IND].DPLLSYNCBUSY.bit.ENABLE) { DBGC(DC_CLK_OSC_INIT_DPLL_SYNC_DISABLE); } - posctrl->Dpll[USE_DPLL_IND].DPLLCTRLB.bit.REFCLK = 2; // select XOSC0 (16MHz) - posctrl->Dpll[USE_DPLL_IND].DPLLCTRLB.bit.DIV = 7; // 16 MHz / (2 * (7 + 1)) = 1 MHz - posctrl->Dpll[USE_DPLL_IND].DPLLRATIO.bit.LDR = PLL_RATIO; // 1 MHz * (PLL_RATIO(47) + 1) = 48MHz + posctrl->Dpll[USE_DPLL_IND].DPLLCTRLB.bit.REFCLK = 2; // select XOSC0 (16MHz) + posctrl->Dpll[USE_DPLL_IND].DPLLCTRLB.bit.DIV = 7; // 16 MHz / (2 * (7 + 1)) = 1 MHz + posctrl->Dpll[USE_DPLL_IND].DPLLRATIO.bit.LDR = PLL_RATIO; // 1 MHz * (PLL_RATIO(47) + 1) = 48MHz while (posctrl->Dpll[USE_DPLL_IND].DPLLSYNCBUSY.bit.DPLLRATIO) { DBGC(DC_CLK_OSC_INIT_DPLL_SYNC_RATIO); } @@ -87,7 +87,7 @@ void CLK_oscctrl_init(void) { system_clks.freq_gclk[0] = system_clks.freq_dpll[0]; usec_delay_mult = system_clks.freq_gclk[0] / (USEC_DELAY_LOOP_CYCLES * 1000000); - if (usec_delay_mult < 1) usec_delay_mult = 1; // Never allow a multiplier of zero + if (usec_delay_mult < 1) usec_delay_mult = 1; // Never allow a multiplier of zero DBGC(DC_CLK_OSC_INIT_COMPLETE); } @@ -240,7 +240,7 @@ uint32_t CLK_enable_timebase(void) { // ptc4->COUNT16.DBGCTRL.bit.DBGRUN = 1; // wave mode - ptc4->COUNT16.WAVE.bit.WAVEGEN = 1; // MFRQ match frequency mode, toggle each CC match + ptc4->COUNT16.WAVE.bit.WAVEGEN = 1; // MFRQ match frequency mode, toggle each CC match // generate event for next stage ptc4->COUNT16.EVCTRL.bit.MCEO0 = 1; @@ -272,9 +272,9 @@ uint32_t CLK_enable_timebase(void) { DBGC(DC_CLK_ENABLE_TIMEBASE_TC0_SYNC_SWRST_2); } // CTRLA as default - ptc0->COUNT32.CTRLA.bit.MODE = 2; // 32 bit mode - ptc0->COUNT32.EVCTRL.bit.TCEI = 1; // enable incoming events - ptc0->COUNT32.EVCTRL.bit.EVACT = 2; // count events + ptc0->COUNT32.CTRLA.bit.MODE = 2; // 32 bit mode + ptc0->COUNT32.EVCTRL.bit.TCEI = 1; // enable incoming events + ptc0->COUNT32.EVCTRL.bit.EVACT = 2; // count events DBGC(DC_CLK_ENABLE_TIMEBASE_TC0_COMPLETE); @@ -284,10 +284,10 @@ uint32_t CLK_enable_timebase(void) { pmclk->APBBMASK.bit.EVSYS_ = 1; pgclk->PCHCTRL[EVSYS_GCLK_ID_0].bit.GEN = GEN_TC45; pgclk->PCHCTRL[EVSYS_GCLK_ID_0].bit.CHEN = 1; - pevsys->USER[44].reg = EVSYS_ID_USER_PORT_EV_0; // TC0 will get event channel 0 - pevsys->Channel[0].CHANNEL.bit.EDGSEL = EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val; // Rising edge - pevsys->Channel[0].CHANNEL.bit.PATH = EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val; // Synchronous - pevsys->Channel[0].CHANNEL.bit.EVGEN = EVSYS_ID_GEN_TC4_MCX_0; // TC4 MC0 + pevsys->USER[44].reg = EVSYS_ID_USER_PORT_EV_0; // TC0 will get event channel 0 + pevsys->Channel[0].CHANNEL.bit.EDGSEL = EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val; // Rising edge + pevsys->Channel[0].CHANNEL.bit.PATH = EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val; // Synchronous + pevsys->Channel[0].CHANNEL.bit.EVGEN = EVSYS_ID_GEN_TC4_MCX_0; // TC4 MC0 DBGC(DC_CLK_ENABLE_TIMEBASE_EVSYS_COMPLETE); @@ -301,15 +301,15 @@ uint32_t CLK_enable_timebase(void) { } void CLK_delay_us(uint32_t usec) { - asm("CBZ R0, return\n\t" // If usec == 0, branch to return label + asm("CBZ R0, return\n\t" // If usec == 0, branch to return label ); - asm("MULS R0, %0\n\t" // Multiply R0(usec) by usec_delay_mult and store in R0 - ".balign 16\n\t" // Ensure loop is aligned for fastest performance - "loop: SUBS R0, #1\n\t" // Subtract 1 from R0 and update flags (1 cycle) - "BNE loop\n\t" // Branch if non-zero to loop label (2 cycles) NOTE: USEC_DELAY_LOOP_CYCLES is the sum of loop cycles - "return:\n\t" // Return label - : // No output registers - : "r"(usec_delay_mult) // For %0 + asm("MULS R0, %0\n\t" // Multiply R0(usec) by usec_delay_mult and store in R0 + ".balign 16\n\t" // Ensure loop is aligned for fastest performance + "loop: SUBS R0, #1\n\t" // Subtract 1 from R0 and update flags (1 cycle) + "BNE loop\n\t" // Branch if non-zero to loop label (2 cycles) NOTE: USEC_DELAY_LOOP_CYCLES is the sum of loop cycles + "return:\n\t" // Return label + : // No output registers + : "r"(usec_delay_mult) // For %0 ); // Note: BX LR generated } diff --git a/tmk_core/protocol/arm_atsam/clks.h b/tmk_core/protocol/arm_atsam/clks.h index 72df3a8e3f..6ee71aff8f 100644 --- a/tmk_core/protocol/arm_atsam/clks.h +++ b/tmk_core/protocol/arm_atsam/clks.h @@ -24,14 +24,14 @@ along with this program. If not, see <http://www.gnu.org/licenses/>. # include "config_led.h" # include "config.h" -#endif // MD_BOOTLOADER +#endif // MD_BOOTLOADER -#define PLL_RATIO 47 // mcu frequency ((X+1)MHz) -#define FREQ_DFLL_DEFAULT 48000000 // DFLL frequency / usb clock -#define FREQ_SPI_DEFAULT 1000000 // spi to 595 shift regs -#define FREQ_I2C0_DEFAULT 100000 // i2c to hub -#define FREQ_I2C1_DEFAULT I2C_HZ // i2c to LED drivers -#define FREQ_TC45_DEFAULT 1000000 // 1 usec resolution +#define PLL_RATIO 47 // mcu frequency ((X+1)MHz) +#define FREQ_DFLL_DEFAULT 48000000 // DFLL frequency / usb clock +#define FREQ_SPI_DEFAULT 1000000 // spi to 595 shift regs +#define FREQ_I2C0_DEFAULT 100000 // i2c to hub +#define FREQ_I2C1_DEFAULT I2C_HZ // i2c to LED drivers +#define FREQ_TC45_DEFAULT 1000000 // 1 usec resolution // I2C1 Set ~Result PWM Time (2x Drivers) // 1000000 1090000 @@ -44,10 +44,10 @@ along with this program. If not, see <http://www.gnu.org/licenses/>. #define FREQ_XOSC0 16000000 -#define CHAN_SERCOM_SPI 2 // shift regs -#define CHAN_SERCOM_I2C0 0 // hub -#define CHAN_SERCOM_I2C1 1 // led drivers -#define CHAN_SERCOM_UART 3 // debug util +#define CHAN_SERCOM_SPI 2 // shift regs +#define CHAN_SERCOM_I2C0 0 // hub +#define CHAN_SERCOM_I2C1 1 // led drivers +#define CHAN_SERCOM_UART 3 // debug util // Generator clock channels #define GEN_DPLL0 0 @@ -86,4 +86,4 @@ uint32_t CLK_set_i2c0_freq(uint8_t sercomn, uint32_t freq); uint32_t CLK_set_i2c1_freq(uint8_t sercomn, uint32_t freq); void CLK_init(void); -#endif // _CLKS_H_ +#endif // _CLKS_H_ diff --git a/tmk_core/protocol/arm_atsam/d51_util.c b/tmk_core/protocol/arm_atsam/d51_util.c index df596f7ba2..5903233085 100644 --- a/tmk_core/protocol/arm_atsam/d51_util.c +++ b/tmk_core/protocol/arm_atsam/d51_util.c @@ -34,7 +34,8 @@ void dbg_print(uint32_t x) { while (t >= 0) { p2 = t; p = 1; - while (p2--) p *= 10; + while (p2--) + p *= 10; n = x / p; x -= n * p; if (!n) { @@ -55,7 +56,7 @@ void dbg_print(uint32_t x) { } for (w = DBG_PAUSE; w; w--) - ; // Long pause after number is complete + ; // Long pause after number is complete } // Display unsigned 32-bit number through debug led @@ -91,7 +92,8 @@ void dled_print(uint32_t x, uint8_t long_pause) { while (t >= 0) { p2 = t; p = 1; - while (p2--) p *= 10; + while (p2--) + p *= 10; n = x / p; x -= n * p; if (!n) { @@ -188,12 +190,12 @@ void debug_code_init(void) { DBGC(DC_UNSET); // Configure Ports for EIC - PORT->Group[DEBUG_BOOT_TRACING_PORT].DIRCLR.reg = 1 << DEBUG_BOOT_TRACING_PIN; // Input - PORT->Group[DEBUG_BOOT_TRACING_PORT].OUTSET.reg = 1 << DEBUG_BOOT_TRACING_PIN; // High - PORT->Group[DEBUG_BOOT_TRACING_PORT].PINCFG[DEBUG_BOOT_TRACING_PIN].bit.INEN = 1; // Input Enable - PORT->Group[DEBUG_BOOT_TRACING_PORT].PINCFG[DEBUG_BOOT_TRACING_PIN].bit.PULLEN = 1; // Pull Enable - PORT->Group[DEBUG_BOOT_TRACING_PORT].PINCFG[DEBUG_BOOT_TRACING_PIN].bit.PMUXEN = 1; // Mux Enable - PORT->Group[DEBUG_BOOT_TRACING_PORT].PMUX[DEBUG_BOOT_TRACING_PIN / 2].bit.PMUXO = 0; // Mux A + PORT->Group[DEBUG_BOOT_TRACING_PORT].DIRCLR.reg = 1 << DEBUG_BOOT_TRACING_PIN; // Input + PORT->Group[DEBUG_BOOT_TRACING_PORT].OUTSET.reg = 1 << DEBUG_BOOT_TRACING_PIN; // High + PORT->Group[DEBUG_BOOT_TRACING_PORT].PINCFG[DEBUG_BOOT_TRACING_PIN].bit.INEN = 1; // Input Enable + PORT->Group[DEBUG_BOOT_TRACING_PORT].PINCFG[DEBUG_BOOT_TRACING_PIN].bit.PULLEN = 1; // Pull Enable + PORT->Group[DEBUG_BOOT_TRACING_PORT].PINCFG[DEBUG_BOOT_TRACING_PIN].bit.PMUXEN = 1; // Mux Enable + PORT->Group[DEBUG_BOOT_TRACING_PORT].PMUX[DEBUG_BOOT_TRACING_PIN / 2].bit.PMUXO = 0; // Mux A // Enable CLK_EIC_APB MCLK->APBAMASK.bit.EIC_ = 1; @@ -223,12 +225,12 @@ void debug_code_disable(void) { } // Default port configuration - PORT->Group[DEBUG_BOOT_TRACING_PORT].DIRCLR.reg = 1 << DEBUG_BOOT_TRACING_PIN; // Input - PORT->Group[DEBUG_BOOT_TRACING_PORT].OUTCLR.reg = 1 << DEBUG_BOOT_TRACING_PIN; // Low - PORT->Group[DEBUG_BOOT_TRACING_PORT].PINCFG[DEBUG_BOOT_TRACING_PIN].bit.INEN = 0; // Input Disable - PORT->Group[DEBUG_BOOT_TRACING_PORT].PINCFG[DEBUG_BOOT_TRACING_PIN].bit.PULLEN = 0; // Pull Disable - PORT->Group[DEBUG_BOOT_TRACING_PORT].PINCFG[DEBUG_BOOT_TRACING_PIN].bit.PMUXEN = 0; // Mux Disable - PORT->Group[DEBUG_BOOT_TRACING_PORT].PMUX[DEBUG_BOOT_TRACING_PIN / 2].bit.PMUXO = 0; // Mux A + PORT->Group[DEBUG_BOOT_TRACING_PORT].DIRCLR.reg = 1 << DEBUG_BOOT_TRACING_PIN; // Input + PORT->Group[DEBUG_BOOT_TRACING_PORT].OUTCLR.reg = 1 << DEBUG_BOOT_TRACING_PIN; // Low + PORT->Group[DEBUG_BOOT_TRACING_PORT].PINCFG[DEBUG_BOOT_TRACING_PIN].bit.INEN = 0; // Input Disable + PORT->Group[DEBUG_BOOT_TRACING_PORT].PINCFG[DEBUG_BOOT_TRACING_PIN].bit.PULLEN = 0; // Pull Disable + PORT->Group[DEBUG_BOOT_TRACING_PORT].PINCFG[DEBUG_BOOT_TRACING_PIN].bit.PMUXEN = 0; // Mux Disable + PORT->Group[DEBUG_BOOT_TRACING_PORT].PMUX[DEBUG_BOOT_TRACING_PIN / 2].bit.PMUXO = 0; // Mux A // Disable CLK_EIC_APB MCLK->APBAMASK.bit.EIC_ = 0; @@ -239,4 +241,4 @@ void debug_code_disable(void) { void debug_code_init(void) {} void debug_code_disable(void) {} -#endif // DEBUG_BOOT_TRACING_ENABLE +#endif // DEBUG_BOOT_TRACING_ENABLE diff --git a/tmk_core/protocol/arm_atsam/d51_util.h b/tmk_core/protocol/arm_atsam/d51_util.h index 89cf338d23..d301e55411 100644 --- a/tmk_core/protocol/arm_atsam/d51_util.h +++ b/tmk_core/protocol/arm_atsam/d51_util.h @@ -219,6 +219,6 @@ enum debug_code_list { # define DBGC(n) \ {} -#endif // DEBUG_BOOT_TRACING_ENABLE +#endif // DEBUG_BOOT_TRACING_ENABLE -#endif //_D51_UTIL_H_ +#endif //_D51_UTIL_H_ diff --git a/tmk_core/protocol/arm_atsam/i2c_master.c b/tmk_core/protocol/arm_atsam/i2c_master.c index af046625f4..6b0b9a703b 100644 --- a/tmk_core/protocol/arm_atsam/i2c_master.c +++ b/tmk_core/protocol/arm_atsam/i2c_master.c @@ -26,21 +26,21 @@ along with this program. If not, see <http://www.gnu.org/licenses/>. # include "config_led.h" # include "matrix.h" -# define I2C_LED_USE_DMA 1 // Set 1 to use background DMA transfers for leds, Set 0 to use inline software transfers +# define I2C_LED_USE_DMA 1 // Set 1 to use background DMA transfers for leds, Set 0 to use inline software transfers DmacDescriptor dmac_desc; DmacDescriptor dmac_desc_wb; -static uint8_t i2c_led_q[I2C_Q_SIZE]; // I2C queue circular buffer -static uint8_t i2c_led_q_s; // Start of circular buffer -static uint8_t i2c_led_q_e; // End of circular buffer -static uint8_t i2c_led_q_full; // Queue full counter for reset +static uint8_t i2c_led_q[I2C_Q_SIZE]; // I2C queue circular buffer +static uint8_t i2c_led_q_s; // Start of circular buffer +static uint8_t i2c_led_q_e; // End of circular buffer +static uint8_t i2c_led_q_full; // Queue full counter for reset -static uint8_t dma_sendbuf[I2C_DMA_MAX_SEND]; // Data being written to I2C +static uint8_t dma_sendbuf[I2C_DMA_MAX_SEND]; // Data being written to I2C volatile uint8_t i2c_led_q_running; -#endif // !defined(MD_BOOTLOADER) && defined(RGB_MATRIX_ENABLE) +#endif // !defined(MD_BOOTLOADER) && defined(RGB_MATRIX_ENABLE) void i2c0_init(void) { DBGC(DC_I2C0_INIT_BEGIN); @@ -56,23 +56,23 @@ void i2c0_init(void) { // I2C // Note: SW Reset handled in CLK_set_i2c0_freq clks.c - SERCOM0->I2CM.CTRLA.bit.MODE = 5; // Set master mode + SERCOM0->I2CM.CTRLA.bit.MODE = 5; // Set master mode - SERCOM0->I2CM.CTRLA.bit.SPEED = 0; // Set to 1 for Fast-mode Plus (FM+) up to 1 MHz - SERCOM0->I2CM.CTRLA.bit.RUNSTDBY = 1; // Enabled + SERCOM0->I2CM.CTRLA.bit.SPEED = 0; // Set to 1 for Fast-mode Plus (FM+) up to 1 MHz + SERCOM0->I2CM.CTRLA.bit.RUNSTDBY = 1; // Enabled - SERCOM0->I2CM.CTRLA.bit.ENABLE = 1; // Enable the device + SERCOM0->I2CM.CTRLA.bit.ENABLE = 1; // Enable the device while (SERCOM0->I2CM.SYNCBUSY.bit.ENABLE) { DBGC(DC_I2C0_INIT_SYNC_ENABLING); - } // Wait for SYNCBUSY.ENABLE to clear + } // Wait for SYNCBUSY.ENABLE to clear - SERCOM0->I2CM.STATUS.bit.BUSSTATE = 1; // Force into IDLE state + SERCOM0->I2CM.STATUS.bit.BUSSTATE = 1; // Force into IDLE state while (SERCOM0->I2CM.SYNCBUSY.bit.SYSOP) { DBGC(DC_I2C0_INIT_SYNC_SYSOP); } while (SERCOM0->I2CM.STATUS.bit.BUSSTATE != 1) { DBGC(DC_I2C0_INIT_WAIT_IDLE); - } // Wait while not idle + } // Wait while not idle DBGC(DC_I2C0_INIT_COMPLETE); } @@ -139,27 +139,27 @@ void i2c1_init(void) { /* I2C */ // Note: SW Reset handled in CLK_set_i2c1_freq clks.c |