diff options
Diffstat (limited to 'tmk_core/protocol/arm_atsam')
54 files changed, 5013 insertions, 6069 deletions
diff --git a/tmk_core/protocol/arm_atsam/adc.c b/tmk_core/protocol/arm_atsam/adc.c index cb5c349b73..1ef1b11d57 100644 --- a/tmk_core/protocol/arm_atsam/adc.c +++ b/tmk_core/protocol/arm_atsam/adc.c @@ -24,76 +24,92 @@ uint16_t v_con_2; uint16_t v_con_1_boot; uint16_t v_con_2_boot; -void ADC0_clock_init(void) -{ +void ADC0_clock_init(void) { DBGC(DC_ADC0_CLOCK_INIT_BEGIN); - MCLK->APBDMASK.bit.ADC0_ = 1; //ADC0 Clock Enable + MCLK->APBDMASK.bit.ADC0_ = 1; // ADC0 Clock Enable - GCLK->PCHCTRL[ADC0_GCLK_ID].bit.GEN = GEN_OSC0; //Select generator clock - GCLK->PCHCTRL[ADC0_GCLK_ID].bit.CHEN = 1; //Enable peripheral clock + GCLK->PCHCTRL[ADC0_GCLK_ID].bit.GEN = GEN_OSC0; // Select generator clock + GCLK->PCHCTRL[ADC0_GCLK_ID].bit.CHEN = 1; // Enable peripheral clock DBGC(DC_ADC0_CLOCK_INIT_COMPLETE); } -void ADC0_init(void) -{ +void ADC0_init(void) { DBGC(DC_ADC0_INIT_BEGIN); - //MCU - PORT->Group[1].DIRCLR.reg = 1 << 0; //PB00 as input 5V - PORT->Group[1].DIRCLR.reg = 1 << 1; //PB01 as input CON2 - PORT->Group[1].DIRCLR.reg = 1 << 2; //PB02 as input CON1 - PORT->Group[1].PMUX[0].bit.PMUXE = 1; //PB00 mux select B ADC 5V - PORT->Group[1].PMUX[0].bit.PMUXO = 1; //PB01 mux select B ADC CON2 - PORT->Group[1].PMUX[1].bit.PMUXE = 1; //PB02 mux select B ADC CON1 - PORT->Group[1].PINCFG[0].bit.PMUXEN = 1; //PB01 mux ADC Enable 5V - PORT->Group[1].PINCFG[1].bit.PMUXEN = 1; //PB01 mux ADC Enable CON2 - PORT->Group[1].PINCFG[2].bit.PMUXEN = 1; //PB02 mux ADC Enable CON1 - - //ADC + // MCU + PORT->Group[1].DIRCLR.reg = 1 << 0; // PB00 as input 5V + PORT->Group[1].DIRCLR.reg = 1 << 1; // PB01 as input CON2 + PORT->Group[1].DIRCLR.reg = 1 << 2; // PB02 as input CON1 + PORT->Group[1].PMUX[0].bit.PMUXE = 1; // PB00 mux select B ADC 5V + PORT->Group[1].PMUX[0].bit.PMUXO = 1; // PB01 mux select B ADC CON2 + PORT->Group[1].PMUX[1].bit.PMUXE = 1; // PB02 mux select B ADC CON1 + PORT->Group[1].PINCFG[0].bit.PMUXEN = 1; // PB01 mux ADC Enable 5V + PORT->Group[1].PINCFG[1].bit.PMUXEN = 1; // PB01 mux ADC Enable CON2 + PORT->Group[1].PINCFG[2].bit.PMUXEN = 1; // PB02 mux ADC Enable CON1 + + // ADC ADC0->CTRLA.bit.SWRST = 1; - while (ADC0->SYNCBUSY.bit.SWRST) { DBGC(DC_ADC0_SWRST_SYNCING_1); } - while (ADC0->CTRLA.bit.SWRST) { DBGC(DC_ADC0_SWRST_SYNCING_2); } - - //Clock divide + while (ADC0->SYNCBUSY.bit.SWRST) { + DBGC(DC_ADC0_SWRST_SYNCING_1); + } + while (ADC0->CTRLA.bit.SWRST) { + DBGC(DC_ADC0_SWRST_SYNCING_2); + } + + // Clock divide ADC0->CTRLA.bit.PRESCALER = ADC_CTRLA_PRESCALER_DIV2_Val; - //Averaging + // Averaging ADC0->AVGCTRL.bit.SAMPLENUM = ADC_AVGCTRL_SAMPLENUM_4_Val; - while (ADC0->SYNCBUSY.bit.AVGCTRL) { DBGC(DC_ADC0_AVGCTRL_SYNCING_1); } - if (ADC0->AVGCTRL.bit.SAMPLENUM == ADC_AVGCTRL_SAMPLENUM_1_Val) ADC0->AVGCTRL.bit.ADJRES = 0; - else if (ADC0->AVGCTRL.bit.SAMPLENUM == ADC_AVGCTRL_SAMPLENUM_2_Val) ADC0->AVGCTRL.bit.ADJRES = 1; - else if (ADC0->AVGCTRL.bit.SAMPLENUM == ADC_AVGCTRL_SAMPLENUM_4_Val) ADC0->AVGCTRL.bit.ADJRES = 2; - else if (ADC0->AVGCTRL.bit.SAMPLENUM == ADC_AVGCTRL_SAMPLENUM_8_Val) ADC0->AVGCTRL.bit.ADJRES = 3; - else ADC0->AVGCTRL.bit.ADJRES = 4; - while (ADC0->SYNCBUSY.bit.AVGCTRL) { DBGC(DC_ADC0_AVGCTRL_SYNCING_2); } - - //Settling - ADC0->SAMPCTRL.bit.SAMPLEN = 45; //Sampling Time Length: 1-63, 1 ADC CLK per - while (ADC0->SYNCBUSY.bit.SAMPCTRL) { DBGC(DC_ADC0_SAMPCTRL_SYNCING_1); } - - //Load factory calibration data - ADC0->CALIB.bit.BIASCOMP = ((*(uint32_t *)ADC0_FUSES_BIASCOMP_ADDR) & ADC0_FUSES_BIASCOMP_Msk) >> ADC0_FUSES_BIASCOMP_Pos; - ADC0->CALIB.bit.BIASR2R = ((*(uint32_t *)ADC0_FUSES_BIASR2R_ADDR) & ADC0_FUSES_BIASR2R_Msk) >> ADC0_FUSES_BIASR2R_Pos; + while (ADC0->SYNCBUSY.bit.AVGCTRL) { + DBGC(DC_ADC0_AVGCTRL_SYNCING_1); + } + if (ADC0->AVGCTRL.bit.SAMPLENUM == ADC_AVGCTRL_SAMPLENUM_1_Val) + ADC0->AVGCTRL.bit.ADJRES = 0; + else if (ADC0->AVGCTRL.bit.SAMPLENUM == ADC_AVGCTRL_SAMPLENUM_2_Val) + ADC0->AVGCTRL.bit.ADJRES = 1; + else if (ADC0->AVGCTRL.bit.SAMPLENUM == ADC_AVGCTRL_SAMPLENUM_4_Val) + ADC0->AVGCTRL.bit.ADJRES = 2; + else if (ADC0->AVGCTRL.bit.SAMPLENUM == ADC_AVGCTRL_SAMPLENUM_8_Val) + ADC0->AVGCTRL.bit.ADJRES = 3; + else + ADC0->AVGCTRL.bit.ADJRES = 4; + while (ADC0->SYNCBUSY.bit.AVGCTRL) { + DBGC(DC_ADC0_AVGCTRL_SYNCING_2); + } + + // Settling + ADC0->SAMPCTRL.bit.SAMPLEN = 45; // Sampling Time Length: 1-63, 1 ADC CLK per + while (ADC0->SYNCBUSY.bit.SAMPCTRL) { + DBGC(DC_ADC0_SAMPCTRL_SYNCING_1); + } + + // Load factory calibration data + ADC0->CALIB.bit.BIASCOMP = ((*(uint32_t *)ADC0_FUSES_BIASCOMP_ADDR) & ADC0_FUSES_BIASCOMP_Msk) >> ADC0_FUSES_BIASCOMP_Pos; + ADC0->CALIB.bit.BIASR2R = ((*(uint32_t *)ADC0_FUSES_BIASR2R_ADDR) & ADC0_FUSES_BIASR2R_Msk) >> ADC0_FUSES_BIASR2R_Pos; ADC0->CALIB.bit.BIASREFBUF = ((*(uint32_t *)ADC0_FUSES_BIASREFBUF_ADDR) & ADC0_FUSES_BIASREFBUF_Msk) >> ADC0_FUSES_BIASREFBUF_Pos; - //Enable + // Enable ADC0->CTRLA.bit.ENABLE = 1; - while (ADC0->SYNCBUSY.bit.ENABLE) { DBGC(DC_ADC0_ENABLE_SYNCING_1); } + while (ADC0->SYNCBUSY.bit.ENABLE) { + DBGC(DC_ADC0_ENABLE_SYNCING_1); + } DBGC(DC_ADC0_INIT_COMPLETE); } -uint16_t adc_get(uint8_t muxpos) -{ +uint16_t adc_get(uint8_t muxpos) { ADC0->INPUTCTRL.bit.MUXPOS = muxpos; - while (ADC0->SYNCBUSY.bit.INPUTCTRL) {} + while (ADC0->SYNCBUSY.bit.INPUTCTRL) { + } ADC0->SWTRIG.bit.START = 1; - while (ADC0->SYNCBUSY.bit.SWTRIG) {} - while (!ADC0->INTFLAG.bit.RESRDY) {} + while (ADC0->SYNCBUSY.bit.SWTRIG) { + } + while (!ADC0->INTFLAG.bit.RESRDY) { + } return ADC0->RESULT.reg; } - diff --git a/tmk_core/protocol/arm_atsam/adc.h b/tmk_core/protocol/arm_atsam/adc.h index 5a90ece3fe..9ab653e5a2 100644 --- a/tmk_core/protocol/arm_atsam/adc.h +++ b/tmk_core/protocol/arm_atsam/adc.h @@ -18,11 +18,11 @@ along with this program. If not, see <http://www.gnu.org/licenses/>. #ifndef _ADC_H_ #define _ADC_H_ -#define ADC_5V_START_LEVEL 2365 +#define ADC_5V_START_LEVEL 2365 -#define ADC_5V ADC_INPUTCTRL_MUXPOS_AIN12_Val -#define ADC_CON1 ADC_INPUTCTRL_MUXPOS_AIN14_Val -#define ADC_CON2 ADC_INPUTCTRL_MUXPOS_AIN13_Val +#define ADC_5V ADC_INPUTCTRL_MUXPOS_AIN12_Val +#define ADC_CON1 ADC_INPUTCTRL_MUXPOS_AIN14_Val +#define ADC_CON2 ADC_INPUTCTRL_MUXPOS_AIN13_Val extern uint16_t v_5v; extern uint16_t v_5v_avg; @@ -34,4 +34,4 @@ extern uint16_t v_con_2_boot; void ADC0_clock_init(void); void ADC0_init(void); -#endif //_ADC_H_ +#endif //_ADC_H_ diff --git a/tmk_core/protocol/arm_atsam/arm_atsam_protocol.h b/tmk_core/protocol/arm_atsam/arm_atsam_protocol.h index 88109186aa..8cb00b872a 100644 --- a/tmk_core/protocol/arm_atsam/arm_atsam_protocol.h +++ b/tmk_core/protocol/arm_atsam/arm_atsam_protocol.h @@ -33,17 +33,16 @@ along with this program. If not, see <http://www.gnu.org/licenses/>. #ifndef MD_BOOTLOADER -#include "main_arm_atsam.h" -#ifdef RGB_MATRIX_ENABLE -#include "led_matrix.h" -#include "rgb_matrix.h" -#endif -#include "issi3733_driver.h" -#include "./usb/compiler.h" -#include "./usb/udc.h" -#include "./usb/udi_cdc.h" - -#endif //MD_BOOTLOADER - -#endif //_ARM_ATSAM_PROTOCOL_H_ - +# include "main_arm_atsam.h" +# ifdef RGB_MATRIX_ENABLE +# include "led_matrix.h" +# include "rgb_matrix.h" +# endif +# include "issi3733_driver.h" +# include "./usb/compiler.h" +# include "./usb/udc.h" +# include "./usb/udi_cdc.h" + +#endif // MD_BOOTLOADER + +#endif //_ARM_ATSAM_PROTOCOL_H_ diff --git a/tmk_core/protocol/arm_atsam/clks.c b/tmk_core/protocol/arm_atsam/clks.c index 1ff318e59b..84ed6d83af 100644 --- a/tmk_core/protocol/arm_atsam/clks.c +++ b/tmk_core/protocol/arm_atsam/clks.c @@ -19,83 +19,105 @@ along with this program. If not, see <http://www.gnu.org/licenses/>. #include <string.h> -volatile clk_t system_clks; +volatile clk_t system_clks; volatile uint64_t ms_clk; -uint32_t usec_delay_mult; -#define USEC_DELAY_LOOP_CYCLES 3 //Sum of instruction cycles in us delay loop +uint32_t usec_delay_mult; +#define USEC_DELAY_LOOP_CYCLES 3 // Sum of instruction cycles in us delay loop -const uint32_t sercom_apbbase[] = {(uint32_t)SERCOM0,(uint32_t)SERCOM1,(uint32_t)SERCOM2,(uint32_t)SERCOM3,(uint32_t)SERCOM4,(uint32_t)SERCOM5}; -const uint8_t sercom_pchan[] = {7, 8, 23, 24, 34, 35}; +const uint32_t sercom_apbbase[] = {(uint32_t)SERCOM0, (uint32_t)SERCOM1, (uint32_t)SERCOM2, (uint32_t)SERCOM3, (uint32_t)SERCOM4, (uint32_t)SERCOM5}; +const uint8_t sercom_pchan[] = {7, 8, 23, 24, 34, 35}; -#define USE_DPLL_IND 0 -#define USE_DPLL_DEF GCLK_SOURCE_DPLL0 +#define USE_DPLL_IND 0 +#define USE_DPLL_DEF GCLK_SOURCE_DPLL0 -void CLK_oscctrl_init(void) -{ +void CLK_oscctrl_init(void) { Oscctrl *posctrl = OSCCTRL; - Gclk *pgclk = GCLK; + Gclk * pgclk = GCLK; DBGC(DC_CLK_OSC_INIT_BEGIN); - //default setup on por - system_clks.freq_dfll = FREQ_DFLL_DEFAULT; + // default setup on por + system_clks.freq_dfll = FREQ_DFLL_DEFAULT; system_clks.freq_gclk[0] = system_clks.freq_dfll; - //configure and startup 16MHz xosc0 - posctrl->XOSCCTRL[0].bit.ENABLE = 0; - posctrl->XOSCCTRL[0].bit.STARTUP = 0xD; - posctrl->XOSCCTRL[0].bit.ENALC = 1; - posctrl->XOSCCTRL[0].bit.IMULT = 5; - posctrl->XOSCCTRL[0].bit.IPTAT = 3; + // configure and startup 16MHz xosc0 + posctrl->XOSCCTRL[0].bit.ENABLE = 0; + posctrl->XOSCCTRL[0].bit.STARTUP = 0xD; + posctrl->XOSCCTRL[0].bit.ENALC = 1; + posctrl->XOSCCTRL[0].bit.IMULT = 5; + posctrl->XOSCCTRL[0].bit.IPTAT = 3; posctrl->XOSCCTRL[0].bit.ONDEMAND = 0; - posctrl->XOSCCTRL[0].bit.XTALEN = 1; - posctrl->XOSCCTRL[0].bit.ENABLE = 1; - while (posctrl->STATUS.bit.XOSCRDY0 == 0) { DBGC(DC_CLK_OSC_INIT_XOSC0_SYNC); } + posctrl->XOSCCTRL[0].bit.XTALEN = 1; + posctrl->XOSCCTRL[0].bit.ENABLE = 1; + while (posctrl->STATUS.bit.XOSCRDY0 == 0) { + DBGC(DC_CLK_OSC_INIT_XOSC0_SYNC); + } system_clks.freq_xosc0 = FREQ_XOSC0; - //configure and startup DPLL + // configure and startup DPLL posctrl->Dpll[USE_DPLL_IND].DPLLCTRLA.bit.ENABLE = 0; - while (posctrl->Dpll[USE_DPLL_IND].DPLLSYNCBUSY.bit.ENABLE) { DBGC(DC_CLK_OSC_INIT_DPLL_SYNC_DISABLE); } - posctrl->Dpll[USE_DPLL_IND].DPLLCTRLB.bit.REFCLK = 2; //select XOSC0 (16MHz) - posctrl->Dpll[USE_DPLL_IND].DPLLCTRLB.bit.DIV = 7; //16 MHz / (2 * (7 + 1)) = 1 MHz - posctrl->Dpll[USE_DPLL_IND].DPLLRATIO.bit.LDR = PLL_RATIO; //1 MHz * (PLL_RATIO(47) + 1) = 48MHz - while (posctrl->Dpll[USE_DPLL_IND].DPLLSYNCBUSY.bit.DPLLRATIO) { DBGC(DC_CLK_OSC_INIT_DPLL_SYNC_RATIO); } + while (posctrl->Dpll[USE_DPLL_IND].DPLLSYNCBUSY.bit.ENABLE) { + DBGC(DC_CLK_OSC_INIT_DPLL_SYNC_DISABLE); + } + posctrl->Dpll[USE_DPLL_IND].DPLLCTRLB.bit.REFCLK = 2; // select XOSC0 (16MHz) + posctrl->Dpll[USE_DPLL_IND].DPLLCTRLB.bit.DIV = 7; // 16 MHz / (2 * (7 + 1)) = 1 MHz + posctrl->Dpll[USE_DPLL_IND].DPLLRATIO.bit.LDR = PLL_RATIO; // 1 MHz * (PLL_RATIO(47) + 1) = 48MHz + while (posctrl->Dpll[USE_DPLL_IND].DPLLSYNCBUSY.bit.DPLLRATIO) { + DBGC(DC_CLK_OSC_INIT_DPLL_SYNC_RATIO); + } posctrl->Dpll[USE_DPLL_IND].DPLLCTRLA.bit.ONDEMAND = 0; - posctrl->Dpll[USE_DPLL_IND].DPLLCTRLA.bit.ENABLE = 1; - while (posctrl->Dpll[USE_DPLL_IND].DPLLSYNCBUSY.bit.ENABLE) { DBGC(DC_CLK_OSC_INIT_DPLL_SYNC_ENABLE); } - while (posctrl->Dpll[USE_DPLL_IND].DPLLSTATUS.bit.LOCK == 0) { DBGC(DC_CLK_OSC_INIT_DPLL_WAIT_LOCK); } - while (posctrl->Dpll[USE_DPLL_IND].DPLLSTATUS.bit.CLKRDY == 0) { DBGC(DC_CLK_OSC_INIT_DPLL_WAIT_CLKRDY); } + posctrl->Dpll[USE_DPLL_IND].DPLLCTRLA.bit.ENABLE = 1; + while (posctrl->Dpll[USE_DPLL_IND].DPLLSYNCBUSY.bit.ENABLE) { + DBGC(DC_CLK_OSC_INIT_DPLL_SYNC_ENABLE); + } + while (posctrl->Dpll[USE_DPLL_IND].DPLLSTATUS.bit.LOCK == 0) { + DBGC(DC_CLK_OSC_INIT_DPLL_WAIT_LOCK); + } + while (posctrl->Dpll[USE_DPLL_IND].DPLLSTATUS.bit.CLKRDY == 0) { + DBGC(DC_CLK_OSC_INIT_DPLL_WAIT_CLKRDY); + } system_clks.freq_dpll[0] = (system_clks.freq_xosc0 / 2 / (posctrl->Dpll[USE_DPLL_IND].DPLLCTRLB.bit.DIV + 1)) * (posctrl->Dpll[USE_DPLL_IND].DPLLRATIO.bit.LDR + 1); - //change gclk0 to DPLL + // change gclk0 to DPLL pgclk->GENCTRL[GEN_DPLL0].bit.SRC = USE_DPLL_DEF; - while (pgclk->SYNCBUSY.bit.GENCTRL0) { DBGC(DC_CLK_OSC_INIT_GCLK_SYNC_GENCTRL0); } + while (pgclk->SYNCBUSY.bit.GENCTRL0) { + DBGC(DC_CLK_OSC_INIT_GCLK_SYNC_GENCTRL0); + } system_clks.freq_gclk[0] = system_clks.freq_dpll[0]; usec_delay_mult = system_clks.freq_gclk[0] / (USEC_DELAY_LOOP_CYCLES * 1000000); - if (usec_delay_mult < 1) usec_delay_mult = 1; //Never allow a multiplier of zero + if (usec_delay_mult < 1) usec_delay_mult = 1; // Never allow a multiplier of zero DBGC(DC_CLK_OSC_INIT_COMPLETE); } -//configure for 1MHz (1 usec timebase) -//call CLK_set_gclk_freq(GEN_TC45, FREQ_TC45_DEFAULT); -uint32_t CLK_set_gclk_freq(uint8_t gclkn, uint32_t freq) -{ +// configure for 1MHz (1 usec timebase) +// call CLK_set_gclk_freq(GEN_TC45, FREQ_TC45_DEFAULT); +uint32_t CLK_set_gclk_freq(uint8_t gclkn, uint32_t freq) { Gclk *pgclk = GCLK; DBGC(DC_CLK_SET_GCLK_FREQ_BEGIN); - while (pgclk->SYNCBUSY.vec.GENCTRL) { DBGC(DC_CLK_SET_GCLK_FREQ_SYNC_1); } + while (pgclk->SYNCBUSY.vec.GENCTRL) { + DBGC(DC_CLK_SET_GCLK_FREQ_SYNC_1); + } pgclk->GENCTRL[gclkn].bit.SRC = USE_DPLL_DEF; - while (pgclk->SYNCBUSY.vec.GENCTRL) { DBGC(DC_CLK_SET_GCLK_FREQ_SYNC_2); } + while (pgclk->SYNCBUSY.vec.GENCTRL) { + DBGC(DC_CLK_SET_GCLK_FREQ_SYNC_2); + } pgclk->GENCTRL[gclkn].bit.DIV = (uint8_t)(system_clks.freq_dpll[0] / freq); - while (pgclk->SYNCBUSY.vec.GENCTRL) { DBGC(DC_CLK_SET_GCLK_FREQ_SYNC_3); } + while (pgclk->SYNCBUSY.vec.GENCTRL) { + DBGC(DC_CLK_SET_GCLK_FREQ_SYNC_3); + } pgclk->GENCTRL[gclkn].bit.DIVSEL = 0; - while (pgclk->SYNCBUSY.vec.GENCTRL) { DBGC(DC_CLK_SET_GCLK_FREQ_SYNC_4); } + while (pgclk->SYNCBUSY.vec.GENCTRL) { + DBGC(DC_CLK_SET_GCLK_FREQ_SYNC_4); + } pgclk->GENCTRL[gclkn].bit.GENEN = 1; - while (pgclk->SYNCBUSY.vec.GENCTRL) { DBGC(DC_CLK_SET_GCLK_FREQ_SYNC_5); } + while (pgclk->SYNCBUSY.vec.GENCTRL) { + DBGC(DC_CLK_SET_GCLK_FREQ_SYNC_5); + } system_clks.freq_gclk[gclkn] = system_clks.freq_dpll[0] / pgclk->GENCTRL[gclkn].bit.DIV; DBGC(DC_CLK_SET_GCLK_FREQ_COMPLETE); @@ -103,29 +125,37 @@ uint32_t CLK_set_gclk_freq(uint8_t gclkn, uint32_t freq) return system_clks.freq_gclk[gclkn]; } -void CLK_init_osc(void) -{ +void CLK_init_osc(void) { uint8_t gclkn = GEN_OSC0; - Gclk *pgclk = GCLK; + Gclk * pgclk = GCLK; DBGC(DC_CLK_INIT_OSC_BEGIN); - while (pgclk->SYNCBUSY.vec.GENCTRL) { DBGC(DC_CLK_INIT_OSC_SYNC_1); } + while (pgclk->SYNCBUSY.vec.GENCTRL) { + DBGC(DC_CLK_INIT_OSC_SYNC_1); + } pgclk->GENCTRL[gclkn].bit.SRC = GCLK_SOURCE_XOSC0; - while (pgclk->SYNCBUSY.vec.GENCTRL) { DBGC(DC_CLK_INIT_OSC_SYNC_2); } + while (pgclk->SYNCBUSY.vec.GENCTRL) { + DBGC(DC_CLK_INIT_OSC_SYNC_2); + } pgclk->GENCTRL[gclkn].bit.DIV = 1; - while (pgclk->SYNCBUSY.vec.GENCTRL) { DBGC(DC_CLK_INIT_OSC_SYNC_3); } + while (pgclk->SYNCBUSY.vec.GENCTRL) { + DBGC(DC_CLK_INIT_OSC_SYNC_3); + } pgclk->GENCTRL[gclkn].bit.DIVSEL = 0; - while (pgclk->SYNCBUSY.vec.GENCTRL) { DBGC(DC_CLK_INIT_OSC_SYNC_4); } + while (pgclk->SYNCBUSY.vec.GENCTRL) { + DBGC(DC_CLK_INIT_OSC_SYNC_4); + } pgclk->GENCTRL[gclkn].bit.GENEN = 1; - while (pgclk->SYNCBUSY.vec.GENCTRL) { DBGC(DC_CLK_INIT_OSC_SYNC_5); } + while (pgclk->SYNCBUSY.vec.GENCTRL) { + DBGC(DC_CLK_INIT_OSC_SYNC_5); + } system_clks.freq_gclk[gclkn] = system_clks.freq_xosc0; DBGC(DC_CLK_INIT_OSC_COMPLETE); } -void CLK_reset_time(void) -{ +void CLK_reset_time(void) { Tc *ptc4 = TC4; Tc *ptc0 = TC0; @@ -133,72 +163,85 @@ void CLK_reset_time(void) DBGC(DC_CLK_RESET_TIME_BEGIN); - //stop counters + // stop counters ptc4->COUNT16.CTRLA.bit.ENABLE = 0; - while (ptc4->COUNT16.SYNCBUSY.bit.ENABLE) {} + while (ptc4->COUNT16.SYNCBUSY.bit.ENABLE) { + } ptc0->COUNT32.CTRLA.bit.ENABLE = 0; - while (ptc0->COUNT32.SYNCBUSY.bit.ENABLE) {} - //zero counters + while (ptc0->COUNT32.SYNCBUSY.bit.ENABLE) { + } + // zero counters ptc4->COUNT16.COUNT.reg = 0; - while (ptc4->COUNT16.SYNCBUSY.bit.COUNT) {} + while (ptc4->COUNT16.SYNCBUSY.bit.COUNT) { + } ptc0->COUNT32.COUNT.reg = 0; - while (ptc0->COUNT32.SYNCBUSY.bit.COUNT) {} - //start counters + while (ptc0->COUNT32.SYNCBUSY.bit.COUNT) { + } + // start counters ptc0->COUNT32.CTRLA.bit.ENABLE = 1; - while (ptc0->COUNT32.SYNCBUSY.bit.ENABLE) {} + while (ptc0->COUNT32.SYNCBUSY.bit.ENABLE) { + } ptc4->COUNT16.CTRLA.bit.ENABLE = 1; - while (ptc4->COUNT16.SYNCBUSY.bit.ENABLE) {} + while (ptc4->COUNT16.SYNCBUSY.bit.ENABLE) { + } DBGC(DC_CLK_RESET_TIME_COMPLETE); } -void TC4_Handler() -{ - if (TC4->COUNT16.INTFLAG.bit.MC0) - { +void TC4_Handler() { + if (TC4->COUNT16.INTFLAG.bit.MC0) { TC4->COUNT16.INTFLAG.reg = TC_INTENCLR_MC0; ms_clk++; } } -uint32_t CLK_enable_timebase(void) -{ - Gclk *pgclk = GCLK; - Mclk *pmclk = MCLK; - Tc *ptc4 = TC4; - Tc *ptc0 = TC0; +uint32_t CLK_enable_timebase(void) { + Gclk * pgclk = GCLK; + Mclk * pmclk = MCLK; + Tc * ptc4 = TC4; + Tc * ptc0 = TC0; Evsys *pevsys = EVSYS; DBGC(DC_CLK_ENABLE_TIMEBASE_BEGIN); - //gclk2 highspeed time base + // gclk2 highspeed time base CLK_set_gclk_freq(GEN_TC45, FREQ_TC45_DEFAULT); CLK_init_osc(); - //unmask TC4, sourcegclk2 to TC4 - pmclk->APBCMASK.bit.TC4_ = 1; - pgclk->PCHCTRL[TC4_GCLK_ID].bit.GEN = GEN_TC45; + // unmask TC4, sourcegclk2 to TC4 + pmclk->APBCMASK.bit.TC4_ = 1; + pgclk->PCHCTRL[TC4_GCLK_ID].bit.GEN = GEN_TC45; pgclk->PCHCTRL[TC4_GCLK_ID].bit.CHEN = 1; - //configure TC4 + // configure TC4 DBGC(DC_CLK_ENABLE_TIMEBASE_TC4_BEGIN); ptc4->COUNT16.CTRLA.bit.ENABLE = 0; - while (ptc4->COUNT16.SYNCBUSY.bit.ENABLE) { DBGC(DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_DISABLE); } + while (ptc4->COUNT16.SYNCBUSY.bit.ENABLE) { + DBGC(DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_DISABLE); + } ptc4->COUNT16.CTRLA.bit.SWRST = 1; - while (ptc4->COUNT16.SYNCBUSY.bit.SWRST) { DBGC(DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_SWRST_1); } - while (ptc4->COUNT16.CTRLA.bit.SWRST) { DBGC(DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_SWRST_2); } + while (ptc4->COUNT16.SYNCBUSY.bit.SWRST) { + DBGC(DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_SWRST_1); + } + while (ptc4->COUNT16.CTRLA.bit.SWRST) { + DBGC(DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_SWRST_2); + } - //CTRLA defaults - //CTRLB as default, counting up + // CTRLA defaults + // CTRLB as default, counting up ptc4->COUNT16.CTRLBCLR.reg = 5; - while (ptc4->COUNT16.SYNCBUSY.bit.CTRLB) { DBGC(DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_CLTRB); } + while (ptc4->COUNT16.SYNCBUSY.bit.CTRLB) { + DBGC(DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_CLTRB); + } ptc4->COUNT16.CC[0].reg = 999; - while (ptc4->COUNT16.SYNCBUSY.bit.CC0) { DBGC(DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_CC0); } - //ptc4->COUNT16.DBGCTRL.bit.DBGRUN = 1; + while (ptc4->COUNT16.SYNCBUSY.bit.CC0) { + DBGC(DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_CC0); + } + // ptc4->COUNT16.DBGCTRL.bit.DBGRUN = 1; - //wave mode - ptc4->COUNT16.WAVE.bit.WAVEGEN = 1; //MFRQ match frequency mode, toggle each CC match - //generate event for next stage + // wave mode + ptc4->COUNT16.WAVE.bit.WAVEGEN = 1; // MFRQ match frequency mode, toggle each CC match + // generate event for next stage ptc4->COUNT16.EVCTRL.bit.MCEO0 = 1; NVIC_EnableIRQ(TC4_IRQn); @@ -206,39 +249,45 @@ uint32_t CLK_enable_timebase(void) DBGC(DC_CLK_ENABLE_TIMEBASE_TC4_COMPLETE); - //unmask TC0,1, sourcegclk2 to TC0,1 - pmclk->APBAMASK.bit.TC0_ = 1; - pgclk->PCHCTRL[TC0_GCLK_ID].bit.GEN = GEN_TC45; + // unmask TC0,1, sourcegclk2 to TC0,1 + pmclk->APBAMASK.bit.TC0_ = 1; + pgclk->PCHCTRL[TC0_GCLK_ID].bit.GEN = GEN_TC45; pgclk->PCHCTRL[TC0_GCLK_ID].bit.CHEN = 1; - pmclk->APBAMASK.bit.TC1_ = 1; - pgclk->PCHCTRL[TC1_GCLK_ID].bit.GEN = GEN_TC45; + pmclk->APBAMASK.bit.TC1_ = 1; + pgclk->PCHCTRL[TC1_GCLK_ID].bit.GEN = GEN_TC45; pgclk->PCHCTRL[TC1_GCLK_ID].bit.CHEN = 1; - //configure TC0 + // configure TC0 DBGC(DC_CLK_ENABLE_TIMEBASE_TC0_BEGIN); ptc0->COUNT32.CTRLA.bit.ENABLE = 0; - while (ptc0->COUNT32.SYNCBUSY.bit.ENABLE) { DBGC(DC_CLK_ENABLE_TIMEBASE_TC0_SYNC_DISABLE); } + while (ptc0->COUNT32.SYNCBUSY.bit.ENABLE) { + DBGC(DC_CLK_ENABLE_TIMEBASE_TC0_SYNC_DISABLE); + } ptc0->COUNT32.CTRLA.bit.SWRST = 1; - while (ptc0->COUNT32.SYNCBUSY.bit.SWRST) { DBGC(DC_CLK_ENABLE_TIMEBASE_TC0_SYNC_SWRST_1); } - while (ptc0->COUNT32.CTRLA.bit.SWRST) { DBGC(DC_CLK_ENABLE_TIMEBASE_TC0_SYNC_SWRST_2); } - //CTRLA as default - ptc0->COUNT32.CTRLA.bit.MODE = 2; //32 bit mode - ptc0->COUNT32.EVCTRL.bit.TCEI = 1; //enable incoming events - ptc0->COUNT32.EVCTRL.bit.EVACT = 2 ; //count events + while (ptc0->COUNT32.SYNCBUSY.bit.SWRST) { + DBGC(DC_CLK_ENABLE_TIMEBASE_TC0_SYNC_SWRST_1); + } + while (ptc0->COUNT32.CTRLA.bit.SWRST) { + DBGC(DC_CLK_ENABLE_TIMEBASE_TC0_SYNC_SWRST_2); + } + // CTRLA as default + ptc0->COUNT32.CTRLA.bit.MODE = 2; // 32 bit mode + ptc0->COUNT32.EVCTRL.bit.TCEI = 1; // enable incoming events + ptc0->COUNT32.EVCTRL.bit.EVACT = 2; // count events DBGC(DC_CLK_ |