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-rw-r--r--data/schemas/keyboard.jsonschema2
-rw-r--r--docs/compatible_microcontrollers.md2
-rw-r--r--keyboards/handwired/onekey/nucleo_h723zg/info.json19
-rwxr-xr-xkeyboards/handwired/onekey/nucleo_h723zg/readme.md5
-rwxr-xr-xkeyboards/handwired/onekey/nucleo_h723zg/rules.mk0
-rw-r--r--lib/python/qmk/constants.py4
-rw-r--r--platforms/chibios/boards/GENERIC_STM32_H723XG/board/board.mk12
-rwxr-xr-xplatforms/chibios/boards/GENERIC_STM32_H723XG/board/extra.c36
-rw-r--r--platforms/chibios/boards/GENERIC_STM32_H723XG/configs/config.h9
-rw-r--r--platforms/chibios/boards/GENERIC_STM32_H723XG/configs/mcuconf.h511
-rw-r--r--platforms/chibios/bootloaders/stm32_dfu.c73
-rw-r--r--platforms/chibios/chibios_config.h6
-rw-r--r--platforms/chibios/mcu_selection.mk39
13 files changed, 702 insertions, 16 deletions
diff --git a/data/schemas/keyboard.jsonschema b/data/schemas/keyboard.jsonschema
index a6213d6a7c..2051a7b8ba 100644
--- a/data/schemas/keyboard.jsonschema
+++ b/data/schemas/keyboard.jsonschema
@@ -71,6 +71,8 @@
"STM32F446",
"STM32G431",
"STM32G474",
+ "STM32H723",
+ "STM32H733",
"STM32L412",
"STM32L422",
"STM32L432",
diff --git a/docs/compatible_microcontrollers.md b/docs/compatible_microcontrollers.md
index cc9c0b7f92..197033f78b 100644
--- a/docs/compatible_microcontrollers.md
+++ b/docs/compatible_microcontrollers.md
@@ -43,6 +43,8 @@ You can also use any ARM chip with USB that [ChibiOS](https://www.chibios.org) s
* [STM32F446](https://www.st.com/en/microcontrollers-microprocessors/stm32f446.html)
* [STM32G431](https://www.st.com/en/microcontrollers-microprocessors/stm32g4x1.html)
* [STM32G474](https://www.st.com/en/microcontrollers-microprocessors/stm32g4x4.html)
+ * [STM32H723](https://www.st.com/en/microcontrollers-microprocessors/stm32h723-733.html)
+ * [STM32H733](https://www.st.com/en/microcontrollers-microprocessors/stm32h723-733.html)
* [STM32L412](https://www.st.com/en/microcontrollers-microprocessors/stm32l4x2.html)
* [STM32L422](https://www.st.com/en/microcontrollers-microprocessors/stm32l4x2.html)
* [STM32L432](https://www.st.com/en/microcontrollers-microprocessors/stm32l4x2.html)
diff --git a/keyboards/handwired/onekey/nucleo_h723zg/info.json b/keyboards/handwired/onekey/nucleo_h723zg/info.json
new file mode 100644
index 0000000000..7596d007b2
--- /dev/null
+++ b/keyboards/handwired/onekey/nucleo_h723zg/info.json
@@ -0,0 +1,19 @@
+{
+ "keyboard_name": "Onekey Nucleo H723ZG",
+ "processor": "STM32H723",
+ "bootloader": "stm32-dfu",
+ "matrix_pins": {
+ "cols": ["A9"],
+ "rows": ["A10"]
+ },
+ "backlight": {
+ "pin": "B8"
+ },
+ "ws2812": {
+ "pin": "A0"
+ },
+ "apa102": {
+ "data_pin": "A0",
+ "clock_pin": "B13"
+ }
+}
diff --git a/keyboards/handwired/onekey/nucleo_h723zg/readme.md b/keyboards/handwired/onekey/nucleo_h723zg/readme.md
new file mode 100755
index 0000000000..97a2da5115
--- /dev/null
+++ b/keyboards/handwired/onekey/nucleo_h723zg/readme.md
@@ -0,0 +1,5 @@
+# ST Microelectronics Nucleo144-H723 onekey
+
+Supported Hardware: <https://www.st.com/en/evaluation-tools/nucleo-h723zg.html>
+
+To trigger keypress, short together pins *A9* and *A10*.
diff --git a/keyboards/handwired/onekey/nucleo_h723zg/rules.mk b/keyboards/handwired/onekey/nucleo_h723zg/rules.mk
new file mode 100755
index 0000000000..e69de29bb2
--- /dev/null
+++ b/keyboards/handwired/onekey/nucleo_h723zg/rules.mk
diff --git a/lib/python/qmk/constants.py b/lib/python/qmk/constants.py
index 04ec4f6a16..d987ebaae7 100644
--- a/lib/python/qmk/constants.py
+++ b/lib/python/qmk/constants.py
@@ -14,7 +14,7 @@ QMK_FIRMWARE_UPSTREAM = 'qmk/qmk_firmware'
MAX_KEYBOARD_SUBFOLDERS = 5
# Supported processor types
-CHIBIOS_PROCESSORS = 'cortex-m0', 'cortex-m0plus', 'cortex-m3', 'cortex-m4', 'MKL26Z64', 'MK20DX128', 'MK20DX256', 'MK64FX512', 'MK66FX1M0', 'RP2040', 'STM32F042', 'STM32F072', 'STM32F103', 'STM32F303', 'STM32F401', 'STM32F405', 'STM32F407', 'STM32F411', 'STM32F446', 'STM32G431', 'STM32G474', 'STM32L412', 'STM32L422', 'STM32L432', 'STM32L433', 'STM32L442', 'STM32L443', 'GD32VF103', 'WB32F3G71', 'WB32FQ95'
+CHIBIOS_PROCESSORS = 'cortex-m0', 'cortex-m0plus', 'cortex-m3', 'cortex-m4', 'MKL26Z64', 'MK20DX128', 'MK20DX256', 'MK64FX512', 'MK66FX1M0', 'RP2040', 'STM32F042', 'STM32F072', 'STM32F103', 'STM32F303', 'STM32F401', 'STM32F405', 'STM32F407', 'STM32F411', 'STM32F446', 'STM32G431', 'STM32G474', 'STM32H723', 'STM32H733', 'STM32L412', 'STM32L422', 'STM32L432', 'STM32L433', 'STM32L442', 'STM32L443', 'GD32VF103', 'WB32F3G71', 'WB32FQ95'
LUFA_PROCESSORS = 'at90usb162', 'atmega16u2', 'atmega32u2', 'atmega16u4', 'atmega32u4', 'at90usb646', 'at90usb647', 'at90usb1286', 'at90usb1287', None
VUSB_PROCESSORS = 'atmega32a', 'atmega328p', 'atmega328', 'attiny85'
@@ -36,6 +36,8 @@ MCU2BOOTLOADER = {
"STM32F446": "stm32-dfu",
"STM32G431": "stm32-dfu",
"STM32G474": "stm32-dfu",
+ "STM32H723": "stm32-dfu",
+ "STM32H733": "stm32-dfu",
"STM32L412": "stm32-dfu",
"STM32L422": "stm32-dfu",
"STM32L432": "stm32-dfu",
diff --git a/platforms/chibios/boards/GENERIC_STM32_H723XG/board/board.mk b/platforms/chibios/boards/GENERIC_STM32_H723XG/board/board.mk
new file mode 100644
index 0000000000..3511f752a9
--- /dev/null
+++ b/platforms/chibios/boards/GENERIC_STM32_H723XG/board/board.mk
@@ -0,0 +1,12 @@
+# List of all the board related files.
+BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO144_H723ZG/board.c
+
+# Extra files
+BOARDSRC += $(BOARD_PATH)/board/extra.c
+
+# Required include directories
+BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO144_H723ZG
+
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC += $(BOARDINC)
diff --git a/platforms/chibios/boards/GENERIC_STM32_H723XG/board/extra.c b/platforms/chibios/boards/GENERIC_STM32_H723XG/board/extra.c
new file mode 100755
index 0000000000..fce0b4abad
--- /dev/null
+++ b/platforms/chibios/boards/GENERIC_STM32_H723XG/board/extra.c
@@ -0,0 +1,36 @@
+// Copyright 2023 Nick Brassel (@tzarc)
+// SPDX-License-Identifier: GPL-2.0-or-later
+#include <hal.h>
+#define BOOTLOADER_MAGIC 0xDEADBEEF
+
+////////////////////////////////////////////////////////////////////////////////
+// Different signalling for bootloader entry
+// - RAM is cleared on reset, so we can't use the usual __ram0_end__ symbol.
+// - Use backup registers in the RTC peripheral to store the magic value instead.
+
+static inline void enable_backup_register_access(void) {
+ PWR->CR1 |= PWR_CR1_DBP;
+}
+
+static inline void disable_backup_register_access(void) {
+ PWR->CR1 &= ~PWR_CR1_DBP;
+}
+
+void bootloader_marker_enable(void) {
+ enable_backup_register_access();
+ RTC->BKP0R = BOOTLOADER_MAGIC;
+ disable_backup_register_access();
+}
+
+bool bootloader_marker_active(void) {
+ enable_backup_register_access();
+ bool ret = RTC->BKP0R == BOOTLOADER_MAGIC;
+ disable_backup_register_access();
+ return ret;
+}
+
+void bootloader_marker_disable(void) {
+ enable_backup_register_access();
+ RTC->BKP0R = 0;
+ disable_backup_register_access();
+}
diff --git a/platforms/chibios/boards/GENERIC_STM32_H723XG/configs/config.h b/platforms/chibios/boards/GENERIC_STM32_H723XG/configs/config.h
new file mode 100644
index 0000000000..f43df29b54
--- /dev/null
+++ b/platforms/chibios/boards/GENERIC_STM32_H723XG/configs/config.h
@@ -0,0 +1,9 @@
+// Copyright 2023 Nick Brassel (@tzarc)
+// SPDX-License-Identifier: GPL-2.0-or-later
+#pragma once
+
+#define USB_DRIVER USBD2
+
+#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP
+# define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE
+#endif
diff --git a/platforms/chibios/boards/GENERIC_STM32_H723XG/configs/mcuconf.h b/platforms/chibios/boards/GENERIC_STM32_H723XG/configs/mcuconf.h
new file mode 100644
index 0000000000..0239ec5273
--- /dev/null
+++ b/platforms/chibios/boards/GENERIC_STM32_H723XG/configs/mcuconf.h
@@ -0,0 +1,511 @@
+/*
+ ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef MCUCONF_H
+#define MCUCONF_H
+
+/*
+ * STM32H723/33/25/35 drivers configuration.
+ * The following settings override the default settings present in
+ * the various device driver implementation headers.
+ * Note that the settings for each driver only have effect if the whole
+ * driver is enabled in halconf.h.
+ *
+ * IRQ priorities:
+ * 15...0 Lowest...Highest.
+ *
+ * DMA priorities:
+ * 0...3 Lowest...Highest.
+ */
+
+#define STM32H7xx_MCUCONF
+#define STM32H723_MCUCONF
+#define STM32H733_MCUCONF
+#define STM32H725_MCUCONF
+#define STM32H735_MCUCONF
+
+/*
+ * General settings.
+ */
+#define STM32_NO_INIT FALSE
+
+/*
+ * Memory attributes settings.
+ */
+#define STM32_NOCACHE_ENABLE FALSE
+#define STM32_NOCACHE_MPU_REGION MPU_REGION_6
+#define STM32_NOCACHE_RBAR 0x24000000U
+#define STM32_NOCACHE_RASR MPU_RASR_SIZE_16K
+
+/*
+ * PWR system settings.
+ * Reading STM32 Reference Manual is required, settings in PWR_CR3 are
+ * very critical.
+ * Register constants are taken from the ST header.
+ */
+#define STM32_VOS STM32_VOS_SCALE0
+#define STM32_PWR_CR1 (PWR_CR1_SVOS_1 | PWR_CR1_SVOS_0)
+#define STM32_PWR_CR2 (PWR_CR2_BREN)
+#define STM32_PWR_CR3 (PWR_CR3_LDOEN | PWR_CR3_USB33DEN)
+#define STM32_PWR_CPUCR 0
+
+/*
+ * Clock tree static settings.
+ * Reading STM32 Reference Manual is required.
+ */
+#define STM32_HSI_ENABLED TRUE
+#define STM32_LSI_ENABLED FALSE
+#define STM32_CSI_ENABLED FALSE
+#define STM32_HSI48_ENABLED TRUE
+#define STM32_HSE_ENABLED TRUE
+#define STM32_LSE_ENABLED FALSE
+#define STM32_HSIDIV STM32_HSIDIV_DIV1
+
+/*
+ * PLLs static settings.
+ * Reading STM32 Reference Manual is required.
+ */
+#define STM32_PLLSRC STM32_PLLSRC_HSE_CK
+#define STM32_PLLCFGR_MASK ~0
+#define STM32_PLL1_ENABLED TRUE
+#define STM32_PLL1_P_ENABLED TRUE
+#define STM32_PLL1_Q_ENABLED TRUE
+#define STM32_PLL1_R_ENABLED TRUE
+#define STM32_PLL1_DIVM_VALUE 4
+#define STM32_PLL1_DIVN_VALUE 275
+#define STM32_PLL1_FRACN_VALUE 0
+#define STM32_PLL1_DIVP_VALUE 1
+#define STM32_PLL1_DIVQ_VALUE 10
+#define STM32_PLL1_DIVR_VALUE 4
+#define STM32_PLL2_ENABLED TRUE
+#define STM32_PLL2_P_ENABLED TRUE
+#define STM32_PLL2_Q_ENABLED TRUE
+#define STM32_PLL2_R_ENABLED TRUE
+#define STM32_PLL2_DIVM_VALUE 4
+#define STM32_PLL2_DIVN_VALUE 400
+#define STM32_PLL2_FRACN_VALUE 0
+#define STM32_PLL2_DIVP_VALUE 40
+#define STM32_PLL2_DIVQ_VALUE 8
+#define STM32_PLL2_DIVR_VALUE 8
+#define STM32_PLL3_ENABLED TRUE
+#define STM32_PLL3_P_ENABLED TRUE
+#define STM32_PLL3_Q_ENABLED TRUE
+#define STM32_PLL3_R_ENABLED TRUE
+#define STM32_PLL3_DIVM_VALUE 4
+#define STM32_PLL3_DIVN_VALUE 240
+#define STM32_PLL3_FRACN_VALUE 0
+#define STM32_PLL3_DIVP_VALUE 10
+#define STM32_PLL3_DIVQ_VALUE 10
+#define STM32_PLL3_DIVR_VALUE 10
+
+/*
+ * Core clocks dynamic settings (can be changed at runtime).
+ * Reading STM32 Reference Manual is required.
+ */
+#define STM32_SW STM32_SW_PLL1_P_CK
+#define STM32_RTCSEL STM32_RTCSEL_LSI_CK
+#define STM32_D1CPRE STM32_D1CPRE_DIV1
+#define STM32_D1HPRE STM32_D1HPRE_DIV2
+#define STM32_D1PPRE3 STM32_D1PPRE3_DIV2
+#define STM32_D2PPRE1 STM32_D2PPRE1_DIV2
+#define STM32_D2PPRE2 STM32_D2PPRE2_DIV2
+#define STM32_D3PPRE4 STM32_D3PPRE4_DIV2
+
+/*
+ * Peripherals clocks static settings.
+ * Reading STM32 Reference Manual is required.
+ */
+#define STM32_MCO1SEL STM32_MCO1SEL_HSI_CK
+#define STM32_MCO1PRE_VALUE 4
+#define STM32_MCO2SEL STM32_MCO2SEL_SYS_CK
+#define STM32_MCO2PRE_VALUE 4
+#define STM32_TIMPRE_ENABLE TRUE
+#define STM32_HRTIMSEL 0
+#define STM32_STOPKERWUCK 0
+#define STM32_STOPWUCK 0
+#define STM32_RTCPRE_VALUE 8
+#define STM32_CKPERSEL STM32_CKPERSEL_HSE_CK
+#define STM32_SDMMCSEL STM32_SDMMCSEL_PLL1_Q_CK
+#define STM32_OCTOSPISEL STM32_OCTOSPISEL_HCLK
+#define STM32_FMCSEL STM32_FMCSEL_HCLK
+#define STM32_SWPSEL STM32_SWPSEL_PCLK1
+#define STM32_FDCANSEL STM32_FDCANSEL_HSE_CK
+#define STM32_DFSDM1SEL STM32_DFSDM1SEL_PCLK2
+#define STM32_SPDIFSEL STM32_SPDIFSEL_PLL1_Q_CK
+#define STM32_SPI45SEL STM32_SPI45SEL_PCLK2
+#define STM32_SPI123SEL STM32_SPI123SEL_PLL1_Q_CK
+#define STM32_SAI1SEL STM32_SAI1SEL_PLL1_Q_CK
+#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
+#define STM32_CECSEL STM32_CECSEL_LSE_CK
+#define STM32_USBSEL STM32_USBSEL_PLL3_Q_CK
+#define STM32_I2C1235SEL STM32_I2C1235SEL_PCLK1
+#define STM32_RNGSEL STM32_RNGSEL_PLL1_Q_CK
+#define STM32_USART16910SEL STM32_USART16910SEL_PCLK2
+#define STM32_USART234578SEL STM32_USART234578SEL_PCLK1
+#define STM32_SPI6SEL STM32_SPI6SEL_PCLK4
+#define STM32_SAI4BSEL STM32_SAI4BSEL_PLL1_Q_CK
+#define STM32_SAI4ASEL STM32_SAI4ASEL_PLL1_Q_CK
+#define STM32_ADCSEL STM32_ADCSEL_PLL2_P_CK
+#define STM32_LPTIM345SEL STM32_LPTIM345SEL_PCLK4
+#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK4
+#define STM32_I2C4SEL STM32_I2C4SEL_PCLK4
+#define STM32_LPUART1SEL STM32_LPUART1SEL_PCLK4
+
+/*
+ * IRQ system settings.
+ */
+#define STM32_IRQ_EXTI0_PRIORITY 6
+#define STM32_IRQ_EXTI1_PRIORITY 6
+#define STM32_IRQ_EXTI2_PRIORITY 6
+#define STM32_IRQ_EXTI3_PRIORITY 6
+#define STM32_IRQ_EXTI4_PRIORITY 6
+#define STM32_IRQ_EXTI5_9_PRIORITY 6
+#define STM32_IRQ_EXTI10_15_PRIORITY 6
+#define STM32_IRQ_EXTI16_PRIORITY 6
+#define STM32_IRQ_EXTI17_PRIORITY 6
+#define STM32_IRQ_EXTI18_PRIORITY 6
+#define STM32_IRQ_EXTI19_PRIORITY 6
+#define STM32_IRQ_EXTI20_21_PRIORITY 6
+
+#define STM32_IRQ_FDCAN1_PRIORITY 10
+#define STM32_IRQ_FDCAN2_PRIORITY 10
+
+#define STM32_IRQ_MDMA_PRIORITY 9
+
+#define STM32_IRQ_OCTOSPI1_PRIORITY 10
+#define STM32_IRQ_OCTOSPI2_PRIORITY 10
+
+#define STM32_IRQ_SDMMC1_PRIORITY 9
+#define STM32_IRQ_SDMMC2_PRIORITY 9
+
+#define STM32_IRQ_TIM1_UP_PRIORITY 7
+#define STM32_IRQ_TIM1_CC_PRIORITY 7
+#define STM32_IRQ_TIM2_PRIORITY 7
+#define STM32_IRQ_TIM3_PRIORITY 7
+#define STM32_IRQ_TIM4_PRIORITY 7
+#define STM32_IRQ_TIM5_PRIORITY 7
+#define STM32_IRQ_TIM6_PRIORITY 7
+#define STM32_IRQ_TIM7_PRIORITY 7
+#define STM32_IRQ_TIM8_BRK_TIM12_PRIORITY 7
+#define STM32_IRQ_TIM8_UP_TIM13_PRIORITY 7
+#define STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY 7
+#define STM32_IRQ_TIM8_CC_PRIORITY 7
+#define STM32_IRQ_TIM15_PRIORITY 7
+#define STM32_IRQ_TIM16_PRIORITY 7
+#define STM32_IRQ_TIM17_PRIORITY 7
+
+#define STM32_IRQ_USART1_PRIORITY 12
+#define STM32_IRQ_USART2_PRIORITY 12
+#define STM32_IRQ_USART3_PRIORITY 12
+#define STM32_IRQ_UART4_PRIORITY 12
+#define STM32_IRQ_UART5_PRIORITY 12
+#define STM32_IRQ_USART6_PRIORITY 12
+#define STM32_IRQ_UART7_PRIORITY 12
+#define STM32_IRQ_UART8_PRIORITY 12
+#define STM32_IRQ_UART9_PRIORITY 12
+#define STM32_IRQ_USART10_PRIORITY 12
+#define STM32_IRQ_LPUART1_PRIORITY 12
+
+/*
+ * ADC driver system settings.
+ */
+#define STM32_ADC_DUAL_MODE FALSE
+#define STM32_ADC_SAMPLES_SIZE 16
+#define STM32_ADC_USE_ADC12 FALSE
+#define STM32_ADC_ADC12_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_ADC_ADC12_DMA_PRIORITY 2
+#define STM32_ADC_ADC12_IRQ_PRIORITY 5
+#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV4
+
+/*
+ * CAN driver system settings.
+ */
+#define STM32_CAN_USE_FDCAN1 FALSE
+#define STM32_CAN_USE_FDCAN2 FALSE
+
+/*
+ * DAC driver system settings.
+ */
+#define STM32_DAC_DUAL_MODE FALSE
+#define STM32_DAC_USE_DAC1_CH1 FALSE
+#define STM32_DAC_USE_DAC1_CH2 FALSE
+#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
+#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
+#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
+#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
+#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+
+/*
+ * GPT driver system settings.
+ */
+#define STM32_GPT_USE_TIM1 FALSE
+#define STM32_GPT_USE_TIM2 FALSE
+#define STM32_GPT_USE_TIM3 FALSE
+#define STM32_GPT_USE_TIM4 FALSE
+#define STM32_GPT_USE_TIM5 FALSE
+#define STM32_GPT_USE_TIM6 FALSE
+#define STM32_GPT_USE_TIM7 FALSE
+#define STM32_GPT_USE_TIM8 FALSE
+#define STM32_GPT_USE_TIM12 FALSE
+#define STM32_GPT_USE_TIM13 FALSE
+#define STM32_GPT_USE_TIM14 FALSE
+#define STM32_GPT_USE_TIM15 FALSE
+#define STM32_GPT_USE_TIM16 FALSE
+#define STM32_GPT_USE_TIM17 FALSE
+
+/*
+ * I2C driver system settings.
+ */
+#define STM32_I2C_USE_I2C1 FALSE
+#define STM32_I2C_USE_I2C2 FALSE
+#define STM32_I2C_USE_I2C3 FALSE
+#define STM32_I2C_USE_I2C4 FALSE
+#define STM32_I2C_BUSY_TIMEOUT 50
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C4_RX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
+#define STM32_I2C_I2C4_TX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
+#define STM32_I2C_I2C1_IRQ_PRIORITY 5
+#define STM32_I2C_I2C2_IRQ_PRIORITY 5
+#define STM32_I2C_I2C3_IRQ_PRIORITY 5
+#define STM32_I2C_I2C4_IRQ_PRIORITY 5
+#define STM32_I2C_I2C1_DMA_PRIORITY 3
+#define STM32_I2C_I2C2_DMA_PRIORITY 3
+#define STM32_I2C_I2C3_DMA_PRIORITY 3
+#define STM32_I2C_I2C4_DMA_PRIORITY 3
+#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
+
+/*
+ * ICU driver system settings.
+ */
+#define STM32_ICU_USE_TIM1 FALSE
+#define STM32_ICU_USE_TIM2 FALSE
+#define STM32_ICU_USE_TIM3 FALSE
+#define STM32_ICU_USE_TIM4 FALSE
+#define STM32_ICU_USE_TIM5 FALSE
+#define STM32_ICU_USE_TIM8 FALSE
+#define STM32_ICU_USE_TIM12 FALSE
+#define STM32_ICU_USE_TIM13 FALSE
+#define STM32_ICU_USE_TIM14 FALSE
+#define STM32_ICU_USE_TIM15 FALSE
+#define STM32_ICU_USE_TIM16 FALSE
+#define STM32_ICU_USE_TIM17 FALSE
+
+/*
+ * MAC driver system settings.
+ */
+#define STM32_MAC_TRANSMIT_BUFFERS 2
+#define STM32_MAC_RECEIVE_BUFFERS 4
+#define STM32_MAC_BUFFERS_SIZE 1522
+#define STM32_MAC_PHY_TIMEOUT 100
+#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
+#define STM32_MAC_ETH1_IRQ_PRIORITY 13
+#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
+
+/*
+ * PWM driver system settings.
+ */
+#define STM32_PWM_USE_TIM1 FALSE
+#define STM32_PWM_USE_TIM2 FALSE
+#define STM32_PWM_USE_TIM3 FALSE
+#define STM32_PWM_USE_TIM4 FALSE
+#define STM32_PWM_USE_TIM5 FALSE
+#define STM32_PWM_USE_TIM8 FALSE
+#define STM32_PWM_USE_TIM12 FALSE
+#define STM32_PWM_USE_TIM13 FALSE
+#define STM32_PWM_USE_TIM14 FALSE
+#define STM32_PWM_USE_TIM15 FALSE
+#define STM32_PWM_USE_TIM16 FALSE
+#define STM32_PWM_USE_TIM17 FALSE
+
+/*
+ * RTC driver system settings.
+ */
+#define STM32_RTC_PRESA_VALUE 32
+#define STM32_RTC_PRESS_VALUE 1024
+#define STM32_RTC_CR_INIT 0
+#define STM32_RTC_TAMPCR_INIT 0
+
+/*
+ * SDC driver system settings.
+ */
+#define STM32_SDC_USE_SDMMC1 FALSE
+#define STM32_SDC_USE_SDMMC2 FALSE
+#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE
+#define STM32_SDC_SDMMC_WRITE_TIMEOUT 10000
+#define STM32_SDC_SDMMC_READ_TIMEOUT 10000
+#define STM32_SDC_SDMMC_CLOCK_DELAY 10
+#define STM32_SDC_SDMMC_PWRSAV TRUE
+
+/*
+ * SERIAL driver system settings.
+ */
+#define STM32_SERIAL_USE_USART1 FALSE
+#define STM32_SERIAL_USE_USART2 FALSE
+#define STM32_SERIAL_USE_USART3 FALSE
+#define STM32_SERIAL_USE_UART4 FALSE
+#define STM32_SERIAL_USE_UART5 FALSE
+#define STM32_SERIAL_USE_USART6 FALSE
+#define STM32_SERIAL_USE_UART7 FALSE
+#define STM32_SERIAL_USE_UART8 FALSE
+#define STM32_SERIAL_USE_UART9 FALSE
+#define STM32_SERIAL_USE_USART10 FALSE
+#define STM32_SERIAL_USE_LPUART1 FALSE
+
+/*
+ * SIO driver system settings.
+ */
+#define STM32_SIO_USE_USART1 FALSE
+#define STM32_SIO_USE_USART2 FALSE
+#define STM32_SIO_USE_USART3 FALSE
+#define STM32_SIO_USE_UART4 FALSE
+#define STM32_SIO_USE_UART5 FALSE
+#define STM32_SIO_USE_USART6 FALSE
+#define STM32_SIO_USE_UART7 FALSE
+#define STM32_SIO_USE_UART8 FALSE
+#define STM32_SIO_USE_UART9 FALSE
+#define STM32_SIO_USE_USART10 FALSE
+#define STM32_SIO_USE_LPUART1 FALSE
+
+/*
+ * SPI driver system settings.
+ */
+#define STM32_SPI_USE_SPI1 FALSE
+#define STM32_SPI_USE_SPI2 FALSE
+#define STM32_SPI_USE_SPI3 FALSE
+#define STM32_SPI_USE_SPI4 FALSE
+#define STM32_SPI_USE_SPI5 FALSE
+#define STM32_SPI_USE_SPI6 FALSE
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI6_RX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
+#define STM32_SPI_SPI6_TX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
+#define STM32_SPI_SPI1_DMA_PRIORITY 1
+#define STM32_SPI_SPI2_DMA_PRIORITY 1
+#define STM32_SPI_SPI3_DMA_PRIORITY 1
+#define STM32_SPI_SPI4_DMA_PRIORITY 1
+#define STM32_SPI_SPI5_DMA_PRIORITY 1
+#define STM32_SPI_SPI6_DMA_PRIORITY 1
+#define STM32_SPI_SPI1_IRQ_PRIORITY 10
+#define STM32_SPI_SPI2_IRQ_PRIORITY 10
+#define STM32_SPI_SPI3_IRQ_PRIORITY 10
+#define STM32_SPI_SPI4_IRQ_PRIORITY 10
+#define STM32_SPI_SPI5_IRQ_PRIORITY 10
+#define STM32_SPI_SPI6_IRQ_PRIORITY 10
+#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
+
+/*
+ * ST driver system settings.
+ */
+#define STM32_ST_IRQ_PRIORITY 8
+#define STM32_ST_USE_TIMER 2
+
+/*
+ * TRNG driver system settings.
+ */
+#define STM32_TRNG_USE_RNG1 FALSE
+
+/*
+ * UART driver system settings.
+ */
+#define STM32_UART_USE_USART1 FALSE
+#define STM32_UART_USE_USART2 FALSE
+#define STM32_UART_USE_USART3 FALSE
+#define STM32_UART_USE_UART4 FALSE
+#define STM32_UART_USE_UART5 FALSE
+#define STM32_UART_USE_USART6 FALSE
+#define STM32_UART_USE_UART7 FALSE
+#define STM32_UART_USE_UART8 FALSE
+#define STM32_UART_USE_UART9 FALSE
+#define STM32_UART_USE_USART10 FALSE
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART7_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART7_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART8_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART8_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART9_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART9_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART10_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART10_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART1_DMA_PRIORITY 0
+#define STM32_UART_USART2_DMA_PRIORITY 0
+#define STM32_UART_USART3_DMA_PRIORITY 0
+#define STM32_UART_UART4_DMA_PRIORITY 0
+#define STM32_UART_UART5_DMA_PRIORITY 0
+#define STM32_UART_USART6_DMA_PRIORITY 0
+#define STM32_UART_UART7_DMA_PRIORITY 0
+#define STM32_UART_UART8_DMA_PRIORITY 0
+#define STM32_UART_UART9_DMA_PRIORITY 0
+#define STM32_UART_USART10_DMA_PRIORITY 0
+#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
+
+/*
+ * USB driver system settings.
+ */
+#define STM32_USB_USE_OTG2 TRUE
+#define STM32_USB_OTG2_IRQ_PRIORITY 14
+#define STM32_USB_OTG2_RX_FIFO_SIZE 1024
+#define STM32_USB_HOST_WAKEUP_DURATION 2
+
+/*
+ * WDG driver system settings.
+ */
+#define STM32_WDG_USE_IWDG FALSE
+
+/*
+ * WSPI driver system settings.
+ */
+#define STM32_WSPI_USE_OCTOSPI1 FALSE
+#define STM32_WSPI_USE_OCTOSPI2 FALSE
+#define STM32_WSPI_OCTOSPI1_PRESCALER_VALUE 1
+#define STM32_WSPI_OCTOSPI2_PRESCALER_VALUE 1
+#define STM32_WSPI_OCTOSPI1_SSHIFT FALSE
+#define STM32_WSPI_OCTOSPI2_SSHIFT FALSE
+#define STM32_WSPI_OCTOSPI1_DHQC FALSE
+#define STM32_WSPI_OCTOSPI2_DHQC FALSE
+#define STM32_WSPI_OCTOSPI1_MDMA_CHANNEL STM32_MDMA_CHANNEL_ID_ANY
+#define STM32_WSPI_OCTOSPI2_MDMA_CHANNEL STM32_MDMA_CHANNEL_ID_ANY
+#define STM32_WSPI_OCTOSPI1_MDMA_PRIORITY 1
+#define STM32_WSPI_OCTOSPI2_MDMA_PRIORITY 1
+#define STM32_WSPI_OCTOSPI1_MDMA_IRQ_PRIORITY 10
+#define STM32_WSPI_OCTOSPI2_MDMA_IRQ_PRIORITY 10
+#define STM32_WSPI_DMA_ERROR_HOOK(wspip) osalSysHalt("MDMA failure")
+
+#endif /* MCUCONF_H */
diff --git a/platforms/chibios/bootloaders/stm32_dfu.c b/platforms/chibios/bootloaders/stm32_dfu.c
index f845bf21e9..8cf640f7f9 100644
--- a/platforms/chibios/bootloaders/stm32_dfu.c
+++ b/platforms/chibios/bootloaders/stm32_dfu.c
@@ -1,4 +1,4 @@
-/* Copyright 2021 QMK
+/* Copyright 2021-2023 QMK
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -15,12 +15,17 @@
*/
#include "bootloader.h"
+#include "util.h"
#include <ch.h>
#include <hal.h>
#include "wait.h"
-extern uint32_t __ram0_end__;
+#ifndef STM32_BOOTLOADER_RAM_SYMBOL
+# define STM32_BOOTLOADER_RAM_SYMBOL __ram0_end__
+#endif
+
+extern uint32_t STM32_BOOTLOADER_RAM_SYMBOL;
#ifndef STM32_BOOTLOADER_DUAL_BANK
# define STM32_BOOTLOADER_DUAL_BANK FALSE
@@ -72,10 +77,25 @@ void enter_bootloader_mode_if_requested(void) {}
/* This code should be checked whether it runs correctly on platforms */
# define SYMVAL(sym) (uint32_t)(((uint8_t *)&(sym)) - ((uint8_t *)0))
# define BOOTLOADER_MAGIC 0xDEADBEEF
-# define MAGIC_ADDR (unsigned long *)(SYMVAL(__ram0_end__) - 4)
+# define MAGIC_ADDR (unsigned long *)(SYMVAL(STM32_BOOTLOADER_RAM_SYMBOL) - 4)
+
+__attribute__((weak)) void bootloader_marker_enable(void) {
+ uint32_t *marker = (uint32_t *)MAGIC_ADDR;
+ *marker = BOOTLOADER_MAGIC; // set magic flag => reset handler will jump into boot loader
+}
+
+__attribute__((weak)) bool bootloader_marker_active(void) {
+ const uint32_t *marker = (const uint32_t *)MAGIC_ADDR;
+ return (*marker == BOOTLOADER_MAGIC) ? true : false;
+}
+
+__attribute__((weak)) void bootloader_marker_disable(void) {
+ uint32_t *marker = (uint32_t *)MAGIC_ADDR;
+ *marker = 0;
+}
__attribute__((weak)) void bootloader_jump(void) {
- *MAGIC_ADDR = BOOTLOADER_MAGIC; // set magic flag => reset handler will jump into boot loader
+ bootloader_marker_enable();
NVIC_SystemReset();
}
@@ -84,18 +104,43 @@ __attribute__((weak)) void mcu_reset(void) {
}
void enter_bootloader_mode_if_requested(void) {
- unsigned long *check = MAGIC_ADDR;
- if (*check == BOOTLOADER_MAGIC) {
- *check = 0;
- __set_CONTROL(0);
- __set_MSP(*(__IO uint32_t *)STM32_BOOTLOADER_ADDRESS);
+ if (bootloader_marker_active()) {
+ bootloader_marker_disable();
+
+ __disable_irq();
+
+# if defined(QMK_MCU_ARCH_CORTEX_M7)
+ SCB_DisableDCache();
+ SCB_DisableICache();
+# endif
+
+# if defined(__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ ARM_MPU_Disable();
+# endif
+
+ SysTick->CTRL = 0;
+ SysTick->VAL = 0;
+ SysTick->LOAD = 0;
+
+ // Clear interrupt enable and interrupt pending registers
+ for (int i = 0; i < ARRAY_SIZE(NVIC->ICER); i++) {
+ NVIC->ICER[i] = 0xFFFFFFFF;
+ NVIC->ICPR[i] = 0xFFFFFFFF;
+ }
+
__enable_irq();
- typedef void (*BootJump_t)(void);
- BootJump_t boot_jump = *(BootJump_t *)(STM32_BOOTLOADER_ADDRESS + 4);
- boot_jump();
- while (1)
- ;
+ struct system_memory_vector_t {
+ uint32_t stack_top;
+ void (*entrypoint)(void);
+ };
+ const struct system_memory_vector_t *bootloader = (const struct system_memory_vector_t *)(STM32_BOOTLOADER_ADDRESS);
+
+ // Jump to bootloader
+ __set_MSP(bootloader->stack_top);
+ bootloader->entrypoint();
+ while (true) {
+ }
}
}
#endif
diff --git a/platforms/chibios/chibios_config.h b/platforms/chibios/chibios_config.h
index 52632a051e..1f8a7842fe 100644
--- a/platforms/chibios/chibios_config.h
+++ b/platforms/chibios/chibios_config.h
@@ -71,7 +71,11 @@
// STM32 compatibility
#if defined(MCU_STM32)
-# define CPU_CLOCK STM32_SYSCLK
+# if defined(STM32_CORE_CK)
+# define CPU_CLOCK STM32_CORE_CK
+# else
+# define CPU_CLOCK STM32_SYSCLK
+# endif
# if defined(STM32F1XX)
# define USE_GPIOV1
diff --git a/platforms/chibios/mcu_selection.mk b/platforms/chibios/mcu_selection.mk
index f14b16b169..5122ed4634 100644
--- a/platforms/chibios/mcu_selection.mk
+++ b/platforms/chibios/mcu_selection.mk
@@ -705,6 +705,45 @@ ifneq (,$(filter $(MCU),STM32L412 STM32L422))
STM32_BOOTLOADER_ADDRESS ?= 0x1FFF0000
endif
+ifneq (,$(filter $(MCU),STM32H723 STM32H733))
+ # Cortex version
+ MCU = cortex-m7
+
+ # ARM version, CORTEX-M0/M1 are 6, CORTEX-M3/M4/M7 are 7
+ ARMV = 7
+
+ ## chip/board settings
+ # - the next two should match the directories in
+ # <chibios[-contrib]>/os/hal/ports/$(MCU_PORT_NAME)/$(MCU_SERIES)
+ # OR
+ # <chibios[-contrib]>/os/hal/ports/$(MCU_FAMILY)/$(MCU_SERIES)
+ MCU_FAMILY = STM32
+ MCU_SERIES = STM32H7xx
+
+ # Linker script to use
+ # - it should exist either in <chibios>/os/common/startup/ARMCMx/compilers/GCC/ld/
+ # or <keyboard_dir>/ld/
+ MCU_LDSCRIPT ?= STM32H723xG_ITCM64k
+
+ # Startup code to use
+ # - it should exist in <chibios>/os/common/startup/ARMCMx/compilers/GCC/mk/
+ MCU_STARTUP ?= stm32h7xx
+
+ # Board: it should exist either in <chibios>/os/hal/boards/,
+ # <keyboard_dir>/boards/, or drivers/boards/
+ BOARD ?= GENERIC_STM32_H723XG
+
+ PLATFORM_NAME ?= platform_type2
+
+ USE_FPU ?= yes
+
+ # UF2 settings
+ UF2_FAMILY ?= STM32H7
+
+ # Bootloader address for STM32 DFU
+ STM32_BOOTLOADER_ADDRESS ?= 0x1FF09800
+endif
+
ifneq ($(findstring WB32F3G71, $(MCU)),)
# Cortex version
MCU = cortex-m3