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| author | Nick Brassel <nick@tzarc.org> | 2022-08-28 14:23:01 +1000 |
|---|---|---|
| committer | Nick Brassel <nick@tzarc.org> | 2022-08-28 14:23:01 +1000 |
| commit | 0a3f7e48690bb2b7b008300a54554979a55be19a (patch) | |
| tree | 7499d52f20040ed7d5a56496ecb81ed114f80719 /keyboards/bastardkb/charybdis/3x5/blackpill/mcuconf.h | |
| parent | fc0bf67f372c38f72c303cdec21b1d4afb5e8cb4 (diff) | |
| parent | 9b5b0722555891ba94f240760ef3a6d4c870fd13 (diff) | |
Merge remote-tracking branch 'upstream/develop'
Diffstat (limited to 'keyboards/bastardkb/charybdis/3x5/blackpill/mcuconf.h')
| -rw-r--r-- | keyboards/bastardkb/charybdis/3x5/blackpill/mcuconf.h | 61 |
1 files changed, 61 insertions, 0 deletions
diff --git a/keyboards/bastardkb/charybdis/3x5/blackpill/mcuconf.h b/keyboards/bastardkb/charybdis/3x5/blackpill/mcuconf.h new file mode 100644 index 0000000000..1615d1bf46 --- /dev/null +++ b/keyboards/bastardkb/charybdis/3x5/blackpill/mcuconf.h @@ -0,0 +1,61 @@ +/* + * Copyright 2020 Nick Brassel (tzarc) + * Copyright 2021 Stefan Kerkmann (@KarlK90) + * Copyright 2021 Charly Delay <charly@codesink.dev> (@0xcharly) + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#pragma once + +#include_next "mcuconf.h" + +#undef STM32_I2C_USE_I2C1 +#define STM32_I2C_USE_I2C1 TRUE + +#undef STM32_I2C_I2C1_RX_DMA_STREAM +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#undef STM32_I2C_I2C1_TX_DMA_STREAM +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) + +#undef STM32_PWM_USE_TIM2 +#define STM32_PWM_USE_TIM2 TRUE + +#undef STM32_PWM_USE_TIM3 +#define STM32_PWM_USE_TIM3 TRUE + +#undef STM32_SPI_USE_SPI1 +#define STM32_SPI_USE_SPI1 TRUE + +#undef STM32_SPI_SPI1_RX_DMA_STREAM +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#undef STM32_SPI_SPI1_TX_DMA_STREAM +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) + +#undef STM32_SERIAL_USE_USART1 +#define STM32_SERIAL_USE_USART1 TRUE + +// #undef STM32_SERIAL_USE_USART2 +// #define STM32_SERIAL_USE_USART2 TRUE + +// #undef STM32_UART_USART2_RX_DMA_STREAM +// #define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +// #undef STM32_UART_USART2_TX_DMA_STREAM +// #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) + +#undef STM32_GPT_USE_TIM4 +#define STM32_GPT_USE_TIM4 TRUE + +#undef STM32_ST_USE_TIMER +#define STM32_ST_USE_TIMER 5 |