Keyboard: Add HS60 V2 (#4250)

* HS60 V2

- Created V1 and V2 folders
- Added V2 ARM configuration

* Problems in paradise

* More touble

* We got it now!

31 files changed, 5231 insertions, 13 deletions

diff --git a/keyboards/hs60/config.h b/keyboards/hs60/v1/config.h
index 31f7c07901..c297a6e191 100644
--- a/keyboards/hs60/config.h
+++ b/keyboards/hs60/v1/config.h
@@ -15,8 +15,7 @@ You should have received a copy of the GNU General Public License
 along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
 
-#ifndef CONFIG_H
-#define CONFIG_H
+#pragma once
 
 #include "config_common.h"
 
@@ -142,5 +141,3 @@ along with this program.  If not, see <http://www.gnu.org/licenses/>.
 #endif
 
 #define DRIVER_LED_TOTAL DRIVER_1_LED_TOTAL + DRIVER_2_LED_TOTAL
-
-#endif
diff --git a/keyboards/hs60/info.json b/keyboards/hs60/v1/info.json
index 677054cc6e..677054cc6e 100644
--- a/keyboards/hs60/info.json
+++ b/keyboards/hs60/v1/info.json
diff --git a/keyboards/hs60/keymaps/ansi/config.h b/keyboards/hs60/v1/keymaps/ansi/config.h
index bab67fd558..f51cc16d85 100644
--- a/keyboards/hs60/keymaps/ansi/config.h
+++ b/keyboards/hs60/v1/keymaps/ansi/config.h
@@ -14,13 +14,8 @@ GNU General Public License for more details.
 You should have received a copy of the GNU General Public License
 along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
-#ifndef CONFIG_USER_H
-#define CONFIG_USER_H
-
-#include "../../config.h"
+#pragma once
 
 /* Include overwrites for specific keymap */
 
 #define HS60_ANSI
-
-#endif
\ No newline at end of file
diff --git a/keyboards/hs60/keymaps/ansi/keymap.c b/keyboards/hs60/v1/keymaps/ansi/keymap.c
index 923af9e2ce..923af9e2ce 100644
--- a/keyboards/hs60/keymaps/ansi/keymap.c
+++ b/keyboards/hs60/v1/keymaps/ansi/keymap.c
diff --git a/keyboards/hs60/keymaps/ansi/readme.md b/keyboards/hs60/v1/keymaps/ansi/readme.md
index fa811319d3..fa811319d3 100644
--- a/keyboards/hs60/keymaps/ansi/readme.md
+++ b/keyboards/hs60/v1/keymaps/ansi/readme.md
diff --git a/keyboards/hs60/keymaps/default/keymap.c b/keyboards/hs60/v1/keymaps/default/keymap.c
index 2a5e823618..2a5e823618 100644
--- a/keyboards/hs60/keymaps/default/keymap.c
+++ b/keyboards/hs60/v1/keymaps/default/keymap.c
diff --git a/keyboards/hs60/keymaps/default/readme.md b/keyboards/hs60/v1/keymaps/default/readme.md
index 9125cb349e..9125cb349e 100644
--- a/keyboards/hs60/keymaps/default/readme.md
+++ b/keyboards/hs60/v1/keymaps/default/readme.md
diff --git a/keyboards/hs60/readme.md b/keyboards/hs60/v1/readme.md
index 939b588286..a77bbc25ca 100644
--- a/keyboards/hs60/readme.md
+++ b/keyboards/hs60/v1/readme.md
@@ -13,6 +13,6 @@ Due to the RGB implementation, the HS60 is currently not compatible with communi
 
 Make example for this keyboard (after setting up your build environment):
 
-    make hs60:default
+    make hs60/v1:default
 
 See [build environment setup](https://docs.qmk.fm/build_environment_setup.html) then the [make instructions](https://docs.qmk.fm/make_instructions.html) for more information.
diff --git a/keyboards/hs60/rules.mk b/keyboards/hs60/v1/rules.mk
index bff9659489..bff9659489 100644
--- a/keyboards/hs60/rules.mk
+++ b/keyboards/hs60/v1/rules.mk
diff --git a/keyboards/hs60/hs60.c b/keyboards/hs60/v1/v1.c
index 169f84b020..882611030b 100644
--- a/keyboards/hs60/hs60.c
+++ b/keyboards/hs60/v1/v1.c
@@ -13,8 +13,7 @@
  * You should have received a copy of the GNU General Public License
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
-#include "hs60.h"
-#include "config.h"
+#include "v1.h"
 
 // Please ignore this is for upcoming features
 /*#ifdef RAW_ENABLE
diff --git a/keyboards/hs60/hs60.h b/keyboards/hs60/v1/v1.h
index 4de781e5fa..4de781e5fa 100644
--- a/keyboards/hs60/hs60.h
+++ b/keyboards/hs60/v1/v1.h
diff --git a/keyboards/hs60/v2/boards/GENERIC_STM32_F303XC/board.c b/keyboards/hs60/v2/boards/GENERIC_STM32_F303XC/board.c
new file mode 100644
index 0000000000..4331155df4
--- /dev/null
+++ b/keyboards/hs60/v2/boards/GENERIC_STM32_F303XC/board.c
@@ -0,0 +1,126 @@
+/*
+    ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+const PALConfig pal_default_config = {
+#if STM32_HAS_GPIOA
+  {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
+   VAL_GPIOA_ODR,   VAL_GPIOA_AFRL,   VAL_GPIOA_AFRH},
+#endif
+#if STM32_HAS_GPIOB
+  {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
+   VAL_GPIOB_ODR,   VAL_GPIOB_AFRL,   VAL_GPIOB_AFRH},
+#endif
+#if STM32_HAS_GPIOC
+  {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
+   VAL_GPIOC_ODR,   VAL_GPIOC_AFRL,   VAL_GPIOC_AFRH},
+#endif
+#if STM32_HAS_GPIOD
+  {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
+   VAL_GPIOD_ODR,   VAL_GPIOD_AFRL,   VAL_GPIOD_AFRH},
+#endif
+#if STM32_HAS_GPIOE
+  {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
+   VAL_GPIOE_ODR,   VAL_GPIOE_AFRL,   VAL_GPIOE_AFRH},
+#endif
+#if STM32_HAS_GPIOF
+  {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
+   VAL_GPIOF_ODR,   VAL_GPIOF_AFRL,   VAL_GPIOF_AFRH},
+#endif
+#if STM32_HAS_GPIOG
+  {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
+   VAL_GPIOG_ODR,   VAL_GPIOG_AFRL,   VAL_GPIOG_AFRH},
+#endif
+#if STM32_HAS_GPIOH
+  {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
+   VAL_GPIOH_ODR,   VAL_GPIOH_AFRL,   VAL_GPIOH_AFRH},
+#endif
+#if STM32_HAS_GPIOI
+  {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
+   VAL_GPIOI_ODR,   VAL_GPIOI_AFRL,   VAL_GPIOI_AFRH}
+#endif
+};
+#endif
+
+void enter_bootloader_mode_if_requested(void);
+
+/**
+ * @brief   Early initialization code.
+ * @details This initialization must be performed just after stack setup
+ *          and before any other initialization.
+ */
+void __early_init(void) {
+  enter_bootloader_mode_if_requested();
+  stm32_clock_init();
+}
+
+#if HAL_USE_SDC || defined(__DOXYGEN__)
+/**
+ * @brief   SDC card detection.
+ */
+bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
+
+  (void)sdcp;
+  /* TODO: Fill the implementation.*/
+  return true;
+}
+
+/**
+ * @brief   SDC card write protection detection.
+ */
+bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
+
+  (void)sdcp;
+  /* TODO: Fill the implementation.*/
+  return false;
+}
+#endif /* HAL_USE_SDC */
+
+#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
+/**
+ * @brief   MMC_SPI card detection.
+ */
+bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+
+  (void)mmcp;
+  /* TODO: Fill the implementation.*/
+  return true;
+}
+
+/**
+ * @brief   MMC_SPI card write protection detection.
+ */
+bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
+
+  (void)mmcp;
+  /* TODO: Fill the implementation.*/
+  return false;
+}
+#endif
+
+/**
+ * @brief   Board-specific initialization code.
+ * @todo    Add your board-specific code, if any.
+ */
+void boardInit(void) {
+}
diff --git a/keyboards/hs60/v2/boards/GENERIC_STM32_F303XC/board.h b/keyboards/hs60/v2/boards/GENERIC_STM32_F303XC/board.h
new file mode 100644
index 0000000000..fb7283add9
--- /dev/null
+++ b/keyboards/hs60/v2/boards/GENERIC_STM32_F303XC/board.h
@@ -0,0 +1,1187 @@
+/*
+    ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for Clueboard 60% Keyboard
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_GENERIC_STM32_F303XC
+#define BOARD_NAME                  "HS60 V2.0 PCB"
+
+/*
+ * Board oscillators-related settings.
+ * NOTE: LSE not fitted.
+ */
+#if !defined(STM32_LSECLK)
+#define STM32_LSECLK                0U
+#endif
+
+#define STM32_LSEDRV                (3U << 3U)
+
+#if !defined(STM32_HSECLK)
+#define STM32_HSECLK                8000000U
+#endif
+
+// #define STM32_HSE_BYPASS
+
+/*
+ * MCU type as defined in the ST header.
+ */
+#define STM32F303xC
+
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_PIN0       0U
+#define GPIOA_PIN1       1U
+#define GPIOA_PIN2       2U
+#define GPIOA_PIN3       3U
+#define GPIOA_PIN4       4U
+#define GPIOA_PIN5       5U
+#define GPIOA_PIN6       6U
+#define GPIOA_PIN7       7U
+#define GPIOA_PIN8       8U
+#define GPIOA_PIN9       9U
+#define GPIOA_PIN10      10U
+#define GPIOA_USB_DM     11U
+#define GPIOA_USB_DP     12U
+#define GPIOA_SWDIO      13U
+#define GPIOA_SWCLK      14U
+#define GPIOA_PIN15      15U
+
+#define GPIOB_PIN0       0U
+#define GPIOB_PIN1       1U
+#define GPIOB_PIN2       2U
+#define GPIOB_PIN3       3U
+#define GPIOB_PIN4       4U
+#define GPIOB_PIN5       5U
+#define GPIOB_PIN6       6U
+#define GPIOB_PIN7       7U
+#define GPIOB_PIN8       8U
+#define GPIOB_PIN9       9U
+#define GPIOB_PIN10      10U
+#define GPIOB_PIN11      11U
+#define GPIOB_PIN12      12U
+#define GPIOB_PIN13      13U
+#define GPIOB_PIN14      14U
+#define GPIOB_PIN15      15U
+
+#define GPIOC_PIN0       0U
+#define GPIOC_PIN1       1U
+#define GPIOC_PIN2       2U
+#define GPIOC_PIN3       3U
+#define GPIOC_PIN4       4U
+#define GPIOC_PIN5       5U
+#define GPIOC_PIN6       6U
+#define GPIOC_PIN7       7U
+#define GPIOC_PIN8       8U
+#define GPIOC_PIN9       9U
+#define GPIOC_PIN10      10U
+#define GPIOC_PIN11      11U
+#define GPIOC_PIN12      12U
+#define GPIOC_PIN13      13U
+#define GPIOC_PIN14      14U
+#define GPIOC_PIN15      15U
+
+#define GPIOD_PIN0       0U
+#define GPIOD_PIN1       1U
+#define GPIOD_PIN2       2U
+#define GPIOD_PIN3       3U
+#define GPIOD_PIN4       4U
+#define GPIOD_PIN5       5U
+#define GPIOD_PIN6       6U
+#define GPIOD_PIN7       7U
+#define GPIOD_PIN8       8U
+#define GPIOD_PIN9       9U
+#define GPIOD_PIN10      10U
+#define GPIOD_PIN11      11U
+#define GPIOD_PIN12      12U
+#define GPIOD_PIN13      13U
+#define GPIOD_PIN14      14U
+#define GPIOD_PIN15      15U
+
+#define GPIOE_PIN0       0U
+#define GPIOE_PIN1       1U
+#define GPIOE_PIN2       2U
+#define GPIOE_PIN3       3U
+#define GPIOE_PIN4       4U
+#define GPIOE_PIN5       5U
+#define GPIOE_PIN6       6U
+#define GPIOE_PIN7       7U
+#define GPIOE_PIN8       8U
+#define GPIOE_PIN9       9U
+#define GPIOE_PIN10      10U
+#define GPIOE_PIN11      11U
+#define GPIOE_PIN12      12U
+#define GPIOE_PIN13      13U
+#define GPIOE_PIN14      14U
+#define GPIOE_PIN15      15U
+
+#define GPIOF_I2C2_SDA   0U
+#define GPIOF_I2C2_SCL   1U
+#define GPIOF_PIN2       2U
+#define GPIOF_PIN3       3U
+#define GPIOF_PIN4       4U
+#define GPIOF_PIN5       5U
+#define GPIOF_PIN6       6U
+#define GPIOF_PIN7       7U
+#define GPIOF_PIN8       8U
+#define GPIOF_PIN9       9U
+#define GPIOF_PIN10      10U
+#define GPIOF_PIN11      11U
+#define GPIOF_PIN12      12U
+#define GPIOF_PIN13      13U
+#define GPIOF_PIN14      14U
+#define GPIOF_PIN15      15U
+
+#define GPIOG_PIN0       0U
+#define GPIOG_PIN1       1U
+#define GPIOG_PIN2       2U
+#define GPIOG_PIN3       3U
+#define GPIOG_PIN4       4U
+#define GPIOG_PIN5       5U
+#define GPIOG_PIN6       6U
+#define GPIOG_PIN7       7U
+#define GPIOG_PIN8       8U
+#define GPIOG_PIN9       9U
+#define GPIOG_PIN10      10U
+#define GPIOG_PIN11      11U
+#define GPIOG_PIN12      12U
+#define GPIOG_PIN13      13U
+#define GPIOG_PIN14      14U
+#define GPIOG_PIN15      15U
+
+#define GPIOH_PIN0       0U
+#define GPIOH_PIN1       1U
+#define GPIOH_PIN2       2U
+#define GPIOH_PIN3       3U
+#define GPIOH_PIN4       4U
+#define GPIOH_PIN5       5U
+#define GPIOH_PIN6       6U
+#define GPIOH_PIN7       7U
+#define GPIOH_PIN8       8U
+#define GPIOH_PIN9       9U
+#define GPIOH_PIN10      10U
+#define GPIOH_PIN11      11U
+#define GPIOH_PIN12      12U
+#define GPIOH_PIN13      13U
+#define GPIOH_PIN14      14U
+#define GPIOH_PIN15      15U
+
+/*
+ * IO lines assignments.
+ */
+#define LINE_L3GD20_SDI             PAL_LINE(GPIOA, 7U)
+#define LINE_USB_DM                 PAL_LINE(GPIOA, 11U)
+#define LINE_USB_DP                 PAL_LINE(GPIOA, 12U)
+#define LINE_SWDIO                  PAL_LINE(GPIOA, 13U)
+#define LINE_SWCLK                  PAL_LINE(GPIOA, 14U)
+
+#define LINE_PIN6               PAL_LINE(GPIOF, 0U)
+#define LINE_PIN7               PAL_LINE(GPIOF, 1U)
+
+#define LINE_CAPS_LOCK               PAL_LINE(GPIOB, 7U)
+
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+#define PIN_MODE_INPUT(n)           (0U << ((n) * 2U))
+#define PIN_MODE_OUTPUT(n)          (1U << ((n) * 2U))
+#define PIN_MODE_ALTERNATE(n)       (2U << ((n) * 2U))
+#define PIN_MODE_ANALOG(n)          (3U << ((n) * 2U))
+#define PIN_ODR_LOW(n)              (0U << (n))
+#define PIN_ODR_HIGH(n)             (1U << (n))
+#define PIN_OTYPE_PUSHPULL(n)       (0U << (n))
+#define PIN_OTYPE_OPENDRAIN(n)      (1U << (n))
+#define PIN_OSPEED_VERYLOW(n)       (0U << ((n) * 2U))
+#define PIN_OSPEED_LOW(n)           (1U << ((n) * 2U))
+#define PIN_OSPEED_MEDIUM(n)        (2U << ((n) * 2U))
+#define PIN_OSPEED_HIGH(n)          (3U << ((n) * 2U))
+#define PIN_PUPDR_FLOATING(n)       (0U << ((n) * 2U))
+#define PIN_PUPDR_PULLUP(n)         (1U << ((n) * 2U))
+#define PIN_PUPDR_PULLDOWN(n)       (2U << ((n) * 2U))
+#define PIN_AFIO_AF(n, v)           ((v) << (((n) % 8U) * 4U))
+
+/*
+ * GPIOA setup:
+ *
+ * PA0  - NC
+ * PA1  - NC
+ * PA2  - COL1
+ * PA3  - COL2
+ * PA4  - SPEAKER1
+ * PA5  - SPEAKER2
+ * PA6  - COL3
+ * PA7  - COL8
+ * PA8  - COL6
+ * PA9  - COL7
+ * PA10 - ROW5
+ * PA11 - USB_DM                    (alternate 14).
+ * PA12 - USB_DP                    (alternate 14).
+ * PA13 - SWDIO                     (alternate 0).
+ * PA14 - SWCLK                     (alternate 0).
+ * PA15 - ROW4
+ */
+#define VAL_GPIOA_MODER             (PIN_MODE_INPUT(GPIOA_PIN0) |         \
+                                     PIN_MODE_ALTERNATE(GPIOA_PIN1) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN5) |   \
+                                     PIN_MODE_INPUT(GPIOA_PIN6) |  \
+                                     PIN_MODE_INPUT(GPIOA_PIN7) |  \
+                                     PIN_MODE_INPUT(GPIOA_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN9) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN10) |          \
+                                     PIN_MODE_ALTERNATE(GPIOA_USB_DM) |     \
+                                     PIN_MODE_ALTERNATE(GPIOA_USB_DP) |     \
+                                     PIN_MODE_ALTERNATE(GPIOA_SWDIO) |      \
+                                     PIN_MODE_ALTERNATE(GPIOA_SWCLK) |      \
+                                     PIN_MODE_INPUT(GPIOA_PIN15))
+#define VAL_GPIOA_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOA_PIN0) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN5) |   \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN6) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN7) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_USB_DM) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_USB_DP) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN15))
+#define VAL_GPIOA_OSPEEDR           (PIN_OSPEED_VERYLOW(GPIOA_PIN0) |     \
+                                     PIN_OSPEED_HIGH(GPIOA_PIN1) |       \
+                                     PIN_OSPEED_VERYLOW(GPIOA_PIN2) |       \
+                                     PIN_OSPEED_VERYLOW(GPIOA_PIN3) |       \
+                                     PIN_OSPEED_VERYLOW(GPIOA_PIN4) |       \
+                                     PIN_OSPEED_VERYLOW(GPIOA_PIN5) |      \
+                                     PIN_OSPEED_VERYLOW(GPIOA_PIN6) |     \
+                                     PIN_OSPEED_VERYLOW(GPIOA_PIN7) |     \
+                                     PIN_OSPEED_VERYLOW(GPIOA_PIN8) |       \
+                                     PIN_OSPEED_VERYLOW(GPIOA_PIN9) |       \
+                                     PIN_OSPEED_VERYLOW(GPIOA_PIN10) |      \
+                                     PIN_OSPEED_HIGH(GPIOA_USB_DM) |        \
+                                     PIN_OSPEED_VERYLOW(GPIOA_USB_DP) |     \
+                                     PIN_OSPEED_HIGH(GPIOA_SWDIO) |         \
+                                     PIN_OSPEED_HIGH(GPIOA_SWCLK) |         \
+                                     PIN_OSPEED_VERYLOW(GPIOA_PIN15))
+#define VAL_GPIOA_PUPDR             (PIN_PUPDR_FLOATING(GPIOA_PIN0) |     \
+                                     PIN_PUPDR_FLOATING(GPIOA_PIN1) |         \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN2) |         \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN3) |         \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN4) |         \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN5) |   \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN6) |    \
+                                     PIN_PUPDR_FLOATING(GPIOA_PIN7) |  \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN8) |         \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN9) |         \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN10) |        \
+                                     PIN_PUPDR_FLOATING(GPIOA_USB_DM) |     \
+                                     PIN_PUPDR_FLOATING(GPIOA_USB_DP) |     \
+                                     PIN_PUPDR_PULLUP(GPIOA_SWDIO) |        \
+                                     PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) |      \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN15))
+#define VAL_GPIOA_ODR               (PIN_ODR_HIGH(GPIOA_PIN0) |           \
+                                     PIN_ODR_HIGH(GPIOA_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN5) |         \
+                                     PIN_ODR_HIGH(GPIOA_PIN6) |        \
+                                     PIN_ODR_HIGH(GPIOA_PIN7) |        \
+                                     PIN_ODR_HIGH(GPIOA_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOA_USB_DM) |           \
+                                     PIN_ODR_HIGH(GPIOA_USB_DP) |           \
+                                     PIN_ODR_HIGH(GPIOA_SWDIO) |            \
+                                     PIN_ODR_HIGH(GPIOA_SWCLK) |            \
+                                     PIN_ODR_HIGH(GPIOA_PIN15))
+#define VAL_GPIOA_AFRL              (PIN_AFIO_AF(GPIOA_PIN0, 0) |         \
+                                     PIN_AFIO_AF(GPIOA_PIN1, 1) |           \
+                                     PIN_AFIO_AF(GPIOA_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_PIN5, 5) |       \
+                                     PIN_AFIO_AF(GPIOA_PIN6, 5) |      \
+                                     PIN_AFIO_AF(GPIOA_PIN7, 5))
+#define VAL_GPIOA_AFRH              (PIN_AFIO_AF(GPIOA_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOA_USB_DM, 14) |        \
+                                     PIN_AFIO_AF(GPIOA_USB_DP, 14) |        \
+                                     PIN_AFIO_AF(GPIOA_SWDIO, 0) |          \
+                                     PIN_AFIO_AF(GPIOA_SWCLK, 0) |          \
+                                     PIN_AFIO_AF(GPIOA_PIN15, 0))
+
+/*
+ * GPIOB setup:
+ *
+ * PB0  - PIN0                      (input pullup).
+ * PB1  - PIN1                      (input pullup).
+ * PB2  - PIN2                      (input pullup).
+ * PB3  - PIN3                       (alternate 0).
+ * PB4  - PIN4                      (input pullup).
+ * PB5  - PIN5                      (input pullup).
+ * PB6  - PIN6 LSM303DLHC_SCL   (alternate 4).
+ * PB7  - PIN7 LSM303DLHC_SDA   (alternate 4).
+ * PB8  - PIN8                      (input pullup).
+ * PB9  - PIN9                      (input pullup).
+ * PB10 - PIN10                     (input pullup).
+ * PB11 - PIN11                     (input pullup).
+ * PB12 - PIN12                     (input pullup).
+ * PB13 - PIN13                     (input pullup).
+ * PB14 - PIN14                     (input pullup).
+ * PB15 - PIN15                     (input pullup).
+ */
+#define VAL_GPIOB_MODER             (PIN_MODE_INPUT(GPIOB_PIN0) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN1) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN2) |           \
+                                     PIN_MODE_ALTERNATE(GPIOB_PIN3) |        \
+                                     PIN_MODE_INPUT(GPIOB_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN5) |           \
+                                     PIN_MODE_ALTERNATE(GPIOB_PIN6) |   \
+                                     PIN_MODE_OUTPUT(GPIOB_PIN7) |   \
+                                     PIN_MODE_INPUT(GPIOB_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN9) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOB_PIN11) |          \
+                                     PIN_MODE_INPUT(GPIOB_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOB_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOB_PIN14) |          \
+                                     PIN_MODE_INPUT(GPIOB_PIN15))
+#define VAL_GPIOB_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN3) |        \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN5) |       \
+                                     PIN_OTYPE_OPENDRAIN(GPIOB_PIN6) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN7) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN14) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN15))
+#define VAL_GPIOB_OSPEEDR           (PIN_OSPEED_VERYLOW(GPIOB_PIN0) |       \
+                                     PIN_OSPEED_VERYLOW(GPIOB_PIN1) |       \
+                                     PIN_OSPEED_VERYLOW(GPIOB_PIN2) |       \
+                                     PIN_OSPEED_HIGH(GPIOB_PIN3) |           \
+                                     PIN_OSPEED_VERYLOW(GPIOB_PIN4) |       \
+                                     PIN_OSPEED_VERYLOW(GPIOB_PIN5) |       \
+                                     PIN_OSPEED_HIGH(GPIOB_PIN6) |      \
+                                     PIN_OSPEED_VERYLOW(GPIOB_PIN7) |      \
+                                     PIN_OSPEED_VERYLOW(GPIOB_PIN8) |       \
+                                     PIN_OSPEED_VERYLOW(GPIOB_PIN9) |       \
+                                     PIN_OSPEED_VERYLOW(GPIOB_PIN10) |      \
+                                     PIN_OSPEED_VERYLOW(GPIOB_PIN11) |      \
+                                     PIN_OSPEED_VERYLOW(GPIOB_PIN12) |      \
+                                     PIN_OSPEED_VERYLOW(GPIOB_PIN13) |      \
+                                     PIN_OSPEED_VERYLOW(GPIOB_PIN14) |      \
+                                     PIN_OSPEED_VERYLOW(GPIOB_PIN15))
+#define VAL_GPIOB_PUPDR             (PIN_PUPDR_PULLUP(GPIOB_PIN0) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN1) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN2) |         \
+                                     PIN_PUPDR_FLOATING(GPIOB_PIN3) |        \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN4) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN5) |         \
+                                     PIN_PUPDR_FLOATING(GPIOB_PIN6) |   \
+                                     PIN_PUPDR_PULLDOWN(GPIOB_PIN7) |   \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN8) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN9) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN10) |        \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN11) |        \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN12) |        \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN13) |        \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN14) |        \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN15))
+#define VAL_GPIOB_ODR               (PIN_ODR_HIGH(GPIOB_PIN0) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN3) |              \
+                                     PIN_ODR_HIGH(GPIOB_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN6) |         \
+                                     PIN_ODR_LOW(GPIOB_PIN7) |         \
+                                     PIN_ODR_HIGH(GPIOB_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOB_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOB_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOB_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOB_PIN14) |            \
+                                     PIN_ODR_HIGH(GPIOB_PIN15))
+#define VAL_GPIOB_AFRL              (PIN_AFIO_AF(GPIOB_PIN0, 0)