adding noah keyboard (#7432)

* adding noah keyboard

* Update keyboards/matrix/noah/config.h

Co-Authored-By: Drashna Jaelre <drashna@live.com>

* Update keyboards/matrix/noah/noah.c

Co-Authored-By: Drashna Jaelre <drashna@live.com>

21 files changed, 5464 insertions, 0 deletions

diff --git a/keyboards/matrix/noah/boards/noah_bd/board.c b/keyboards/matrix/noah/boards/noah_bd/board.c
new file mode 100644
index 0000000000..7fd6a60b5f
--- /dev/null
+++ b/keyboards/matrix/noah/boards/noah_bd/board.c
@@ -0,0 +1,131 @@
+/*
+    ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/*
+ * This file has been automatically generated using ChibiStudio board
+ * generator plugin. Do not edit manually.
+ */
+
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+const PALConfig pal_default_config = {
+#if STM32_HAS_GPIOA
+  {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
+   VAL_GPIOA_ODR,   VAL_GPIOA_AFRL,   VAL_GPIOA_AFRH},
+#endif
+#if STM32_HAS_GPIOB
+  {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
+   VAL_GPIOB_ODR,   VAL_GPIOB_AFRL,   VAL_GPIOB_AFRH},
+#endif
+#if STM32_HAS_GPIOC
+  {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
+   VAL_GPIOC_ODR,   VAL_GPIOC_AFRL,   VAL_GPIOC_AFRH},
+#endif
+#if STM32_HAS_GPIOD
+  {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
+   VAL_GPIOD_ODR,   VAL_GPIOD_AFRL,   VAL_GPIOD_AFRH},
+#endif
+#if STM32_HAS_GPIOE
+  {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
+   VAL_GPIOE_ODR,   VAL_GPIOE_AFRL,   VAL_GPIOE_AFRH},
+#endif
+#if STM32_HAS_GPIOF
+  {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
+   VAL_GPIOF_ODR,   VAL_GPIOF_AFRL,   VAL_GPIOF_AFRH},
+#endif
+#if STM32_HAS_GPIOG
+  {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
+   VAL_GPIOG_ODR,   VAL_GPIOG_AFRL,   VAL_GPIOG_AFRH},
+#endif
+#if STM32_HAS_GPIOH
+  {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
+   VAL_GPIOH_ODR,   VAL_GPIOH_AFRL,   VAL_GPIOH_AFRH},
+#endif
+#if STM32_HAS_GPIOI
+  {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
+   VAL_GPIOI_ODR,   VAL_GPIOI_AFRL,   VAL_GPIOI_AFRH}
+#endif
+};
+#endif
+
+void enter_bootloader_mode_if_requested(void);
+
+/**
+ * @brief   Early initialization code.
+ * @details This initialization must be performed just after stack setup
+ *          and before any other initialization.
+ */
+void __early_init(void) {
+  enter_bootloader_mode_if_requested();
+  stm32_clock_init();
+}
+
+#if HAL_USE_SDC || defined(__DOXYGEN__)
+/**
+ * @brief   SDC card detection.
+ */
+bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
+
+  (void)sdcp;
+  /* TODO: Fill the implementation.*/
+  return true;
+}
+
+/**
+ * @brief   SDC card write protection detection.
+ */
+bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
+
+  (void)sdcp;
+  /* TODO: Fill the implementation.*/
+  return false;
+}
+#endif /* HAL_USE_SDC */
+
+#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
+/**
+ * @brief   MMC_SPI card detection.
+ */
+bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+
+  (void)mmcp;
+  /* TODO: Fill the implementation.*/
+  return true;
+}
+
+/**
+ * @brief   MMC_SPI card write protection detection.
+ */
+bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
+
+  (void)mmcp;
+  /* TODO: Fill the implementation.*/
+  return false;
+}
+#endif
+
+/**
+ * @brief   Board-specific initialization code.
+ * @todo    Add your board-specific code, if any.
+ */
+void boardInit(void) {
+}
diff --git a/keyboards/matrix/noah/boards/noah_bd/board.h b/keyboards/matrix/noah/boards/noah_bd/board.h
new file mode 100644
index 0000000000..37d1d13623
--- /dev/null
+++ b/keyboards/matrix/noah/boards/noah_bd/board.h
@@ -0,0 +1,1336 @@
+/*
+    ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/*
+ * This file has been automatically generated using ChibiStudio board
+ * generator plugin. Do not edit manually.
+ */
+
+#ifndef BOARD_H
+#define BOARD_H
+
+/*
+ * Setup for Matrix M65 board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_MATRIX_NOAH
+#define BOARD_NAME                  "Matrix noah65 keyboard"
+#define BOARD_OTG_NOVBUSSENS
+
+/*
+ * Board oscillators-related settings.
+ * NOTE: LSE not fitted.
+ */
+#if !defined(STM32_LSECLK)
+#define STM32_LSECLK                0U
+#endif
+
+#if !defined(STM32_HSECLK)
+#define STM32_HSECLK                8000000U
+#endif
+
+//#define STM32_HSE_BYPASS
+
+/*
+ * Board voltages.
+ * Required for performance limits calculation.
+ */
+#define STM32_VDD                   300U
+
+/*
+ * MCU type as defined in the ST header.
+ */
+#define STM32F411xE
+
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_PIN0                  0U
+#define GPIOA_PIN1                  1U
+#define GPIOA_PIN2                  2U
+#define GPIOA_PIN3                  3U
+#define GPIOA_PIN4                  4U
+#define GPIOA_SCK                   5U
+#define GPIOA_MISO                  6U
+#define GPIOA_MOSI                  7U
+#define GPIOA_PIN8                  8U
+#define GPIOA_PIN9                  9U
+#define GPIOA_PIN10                 10U
+#define GPIOA_OTG_FS_DM             11U
+#define GPIOA_OTG_FS_DP             12U
+#define GPIOA_SWDIO                 13U
+#define GPIOA_SWCLK                 14U
+#define GPIOA_PIN15                 15U
+
+#define GPIOB_PIN0                  0U
+#define GPIOB_PIN1                  1U
+#define GPIOB_PIN2                  2U
+#define GPIOB_SWO                   3U
+#define GPIOB_PIN4                  4U
+#define GPIOB_PIN5                  5U
+#define GPIOB_PIN6                  6U
+#define GPIOB_PIN7                  7U
+#define GPIOB_PIN8                  8U
+#define GPIOB_PIN9                  9U
+#define GPIOB_PIN10                 10U
+#define GPIOB_PIN11                 11U
+#define GPIOB_PIN12                 12U
+#define GPIOB_PIN13                 13U
+#define GPIOB_PIN14                 14U
+#define GPIOB_PIN15                 15U
+
+#define GPIOC_PIN0                  0U
+#define GPIOC_PIN1                  1U
+#define GPIOC_PIN2                  2U
+#define GPIOC_PIN3                  3U
+#define GPIOC_PIN4                  4U
+#define GPIOC_PIN5                  5U
+#define GPIOC_PIN6                  6U
+#define GPIOC_PIN7                  7U
+#define GPIOC_PIN8                  8U
+#define GPIOC_PIN9                  9U
+#define GPIOC_PIN10                 10U
+#define GPIOC_PIN11                 11U
+#define GPIOC_PIN12                 12U
+#define GPIOC_PIN13                 13U
+#define GPIOC_PIN14                 14U
+#define GPIOC_PIN15                 15U
+
+#define GPIOD_PIN0                  0U
+#define GPIOD_PIN1                  1U
+#define GPIOD_PIN2                  2U
+#define GPIOD_PIN3                  3U
+#define GPIOD_PIN4                  4U
+#define GPIOD_PIN5                  5U
+#define GPIOD_PIN6                  6U
+#define GPIOD_PIN7                  7U
+#define GPIOD_PIN8                  8U
+#define GPIOD_PIN9                  9U
+#define GPIOD_PIN10                 10U
+#define GPIOD_PIN11                 11U
+#define GPIOD_PIN12                 12U
+#define GPIOD_PIN13                 13U
+#define GPIOD_PIN14                 14U
+#define GPIOD_PIN15                 15U
+
+#define GPIOE_PIN0                  0U
+#define GPIOE_PIN1                  1U
+#define GPIOE_PIN2                  2U
+#define GPIOE_PIN3                  3U
+#define GPIOE_PIN4                  4U
+#define GPIOE_PIN5                  5U
+#define GPIOE_PIN6                  6U
+#define GPIOE_PIN7                  7U
+#define GPIOE_PIN8                  8U
+#define GPIOE_PIN9                  9U
+#define GPIOE_PIN10                 10U
+#define GPIOE_PIN11                 11U
+#define GPIOE_PIN12                 12U
+#define GPIOE_PIN13                 13U
+#define GPIOE_PIN14                 14U
+#define GPIOE_PIN15                 15U
+
+#define GPIOF_PIN0                  0U
+#define GPIOF_PIN1                  1U
+#define GPIOF_PIN2                  2U
+#define GPIOF_PIN3                  3U
+#define GPIOF_PIN4                  4U
+#define GPIOF_PIN5                  5U
+#define GPIOF_PIN6                  6U
+#define GPIOF_PIN7                  7U
+#define GPIOF_PIN8                  8U
+#define GPIOF_PIN9                  9U
+#define GPIOF_PIN10                 10U
+#define GPIOF_PIN11                 11U
+#define GPIOF_PIN12                 12U
+#define GPIOF_PIN13                 13U
+#define GPIOF_PIN14                 14U
+#define GPIOF_PIN15                 15U
+
+#define GPIOG_PIN0                  0U
+#define GPIOG_PIN1                  1U
+#define GPIOG_PIN2                  2U
+#define GPIOG_PIN3                  3U
+#define GPIOG_PIN4                  4U
+#define GPIOG_PIN5                  5U
+#define GPIOG_PIN6                  6U
+#define GPIOG_PIN7                  7U
+#define GPIOG_PIN8                  8U
+#define GPIOG_PIN9                  9U
+#define GPIOG_PIN10                 10U
+#define GPIOG_PIN11                 11U
+#define GPIOG_PIN12                 12U
+#define GPIOG_PIN13                 13U
+#define GPIOG_PIN14                 14U
+#define GPIOG_PIN15                 15U
+
+#define GPIOH_OSC_IN                0U
+#define GPIOH_OSC_OUT               1U
+#define GPIOH_PIN2                  2U
+#define GPIOH_PIN3                  3U
+#define GPIOH_PIN4                  4U
+#define GPIOH_PIN5                  5U
+#define GPIOH_PIN6                  6U
+#define GPIOH_PIN7                  7U
+#define GPIOH_PIN8                  8U
+#define GPIOH_PIN9                  9U
+#define GPIOH_PIN10                 10U
+#define GPIOH_PIN11                 11U
+#define GPIOH_PIN12                 12U
+#define GPIOH_PIN13                 13U
+#define GPIOH_PIN14                 14U
+#define GPIOH_PIN15                 15U
+
+#define GPIOI_PIN0                  0U
+#define GPIOI_PIN1                  1U
+#define GPIOI_PIN2                  2U
+#define GPIOI_PIN3                  3U
+#define GPIOI_PIN4                  4U
+#define GPIOI_PIN5                  5U
+#define GPIOI_PIN6                  6U
+#define GPIOI_PIN7                  7U
+#define GPIOI_PIN8                  8U
+#define GPIOI_PIN9                  9U
+#define GPIOI_PIN10                 10U
+#define GPIOI_PIN11                 11U
+#define GPIOI_PIN12                 12U
+#define GPIOI_PIN13                 13U
+#define GPIOI_PIN14                 14U
+#define GPIOI_PIN15                 15U
+
+/*
+ * IO lines assignments.
+ */
+#define LINE_ROW_1                  PAL_LINE(GPIOB, 0U)
+#define LINE_ROW_2                  PAL_LINE(GPIOA, 1U)
+#define LINE_ROW_3                  PAL_LINE(GPIOC, 14U)
+#define LINE_ROW_4                  PAL_LINE(GPIOC, 13U)
+#define LINE_ROW_5                  PAL_LINE(GPIOA, 0U)
+
+#define LINE_COL_1                  PAL_LINE(GPIOC, 15U)
+#define LINE_COL_2                  PAL_LINE(GPIOB, 10U)
+#define LINE_COL_3                  PAL_LINE(GPIOB, 7U)
+#define LINE_COL_4                  PAL_LINE(GPIOB, 6U)
+#define LINE_COL_5                  PAL_LINE(GPIOB, 5U)
+#define LINE_COL_6                  PAL_LINE(GPIOB, 4U)
+#define LINE_COL_7                  PAL_LINE(GPIOA, 15U)
+#define LINE_COL_8                  PAL_LINE(GPIOA, 10U)
+#define LINE_COL_9                  PAL_LINE(GPIOA, 9U)
+#define LINE_COL_10                 PAL_LINE(GPIOA, 8U)
+#define LINE_COL_11                 PAL_LINE(GPIOB, 15U)
+#define LINE_COL_12                 PAL_LINE(GPIOB, 14U)
+#define LINE_COL_13                 PAL_LINE(GPIOB, 13U)
+#define LINE_COL_14                 PAL_LINE(GPIOB, 12U)
+#define LINE_COL_15                 PAL_LINE(GPIOB, 2U)
+
+// u2u lines
+#define LINE_U2U_RST                PAL_LINE(GPIOA, 2U)
+#define LINE_U2U_IRQ                PAL_LINE(GPIOA, 3U)
+#define LINE_U2U_CS                 PAL_LINE(GPIOA, 4U)
+#define LINE_U2U_SCK                PAL_LINE(GPIOA, 5U)
+#define LINE_U2U_MISO               PAL_LINE(GPIOA, 6U)
+#define LINE_U2U_MOSI               PAL_LINE(GPIOA, 7U)
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+#define PIN_MODE_INPUT(n)           (0U << ((n) * 2U))
+#define PIN_MODE_OUTPUT(n)          (1U << ((n) * 2U))
+#define PIN_MODE_ALTERNATE(n)       (2U << ((n) * 2U))
+#define PIN_MODE_ANALOG(n)          (3U << ((n) * 2U))
+#define PIN_ODR_LOW(n)              (0U << (n))
+#define PIN_ODR_HIGH(n)             (1U << (n))
+#define PIN_OTYPE_PUSHPULL(n)       (0U << (n))
+#define PIN_OTYPE_OPENDRAIN(n)      (1U << (n))
+#define PIN_OSPEED_VERYLOW(n)       (0U << ((n) * 2U))
+#define PIN_OSPEED_LOW(n)           (1U << ((n) * 2U))
+#define PIN_OSPEED_MEDIUM(n)        (2U << ((n) * 2U))
+#define PIN_OSPEED_HIGH(n)          (3U << ((n) * 2U))
+#define PIN_PUPDR_FLOATING(n)       (0U << ((n) * 2U))
+#define PIN_PUPDR_PULLUP(n)         (1U << ((n) * 2U))
+#define PIN_PUPDR_PULLDOWN(n)       (2U << ((n) * 2U))
+#define PIN_AFIO_AF(n, v)           ((v) << (((n) % 8U) * 4U))
+
+/*
+ * GPIOA setup:
+ *
+ * PA0  -                           (input pullup).
+ * PA1  -                           (input pullup).
+ * PA2  -                           (input pullup).
+ * PA3  -                           (input pullup).
+ * PA4  -                           (input pullup).
+ * PA5  - SPI SCK                   (alternate 5).
+ * PA6  - SPI MISO                  (alternate 5).
+ * PA7  - SPI MOSI                  (alternate 5).
+ * PA8  -                           (input pullup).
+ * PA9  -                           (input pullup).
+ * PA10 -                           (input pullup).
+ * PA11 - OTG_FS_DM                 (alternate 10).
+ * PA12 - OTG_FS_DP                 (alternate 10).
+ * PA13 - SWDIO                     (alternate 0).
+ * PA14 - SWCLK                     (alternate 0).
+ * PA15 -                           (input pullup).
+ */
+#define VAL_GPIOA_MODER             (PIN_MODE_INPUT(GPIOA_PIN0) |         \
+                                     PIN_MODE_INPUT(GPIOA_PIN1) |         \
+                                     PIN_MODE_INPUT(GPIOA_PIN2) |     \
+                                     PIN_MODE_INPUT(GPIOA_PIN3) |     \
+                                     PIN_MODE_INPUT(GPIOA_PIN4) |         \
+                                     PIN_MODE_ALTERNATE(GPIOA_SCK) |     \
+                                     PIN_MODE_ALTERNATE(GPIOA_MISO) |        \
+                                     PIN_MODE_ALTERNATE(GPIOA_MOSI) |        \
+                                     PIN_MODE_INPUT(GPIOA_PIN8) |         \
+                                     PIN_MODE_INPUT(GPIOA_PIN9) |         \
+                                     PIN_MODE_INPUT(GPIOA_PIN10) |         \
+                                     PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DM) |  \
+                                     PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DP) |  \
+                                     PIN_MODE_ALTERNATE(GPIOA_SWDIO) |      \
+                                     PIN_MODE_ALTERNATE(GPIOA_SWCLK) |      \
+                                     PIN_MODE_INPUT(GPIOA_PIN15))
+#define VAL_GPIOA_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOA_PIN0) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN1) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN2) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN3) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN4) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_SCK) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_MISO) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_MOSI) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN8) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN9) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN10) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DM) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DP) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN15))
+#define VAL_GPIOA_OSPEEDR           (PIN_OSPEED_VERYLOW(GPIOA_PIN0) |        \
+                                     PIN_OSPEED_VERYLOW(GPIOA_PIN1) |        \
+                                     PIN_OSPEED_VERYLOW(GPIOA_PIN2) |      \
+                                     PIN_OSPEED_VERYLOW(GPIOA_PIN3) |      \
+                                     PIN_OSPEED_VERYLOW(GPIOA_PIN4) |        \
+                                     PIN_OSPEED_HIGH(GPIOA_SCK) |   \
+                                     PIN_OSPEED_HIGH(GPIOA_MISO) |       \
+                                     PIN_OSPEED_HIGH(GPIOA_MOSI) |       \
+                                     PIN_OSPEED_VERYLOW(GPIOA_PIN8) |        \
+                                     PIN_OSPEED_VERYLOW(GPIOA_PIN9) |        \
+                                     PIN_OSPEED_VERYLOW(GPIOA_PIN10) |        \
+                                     PIN_OSPEED_HIGH(GPIOA_OTG_FS_DM) |     \
+                                     PIN_OSPEED_HIGH(GPIOA_OTG_FS_DP) |     \
+                                     PIN_OSPEED_HIGH(GPIOA_SWDIO) |         \
+                                     PIN_OSPEED_HIGH(GPIOA_SWCLK) |         \
+                                     PIN_OSPEED_VERYLOW(GPIOA_PIN15))
+#define VAL_GPIOA_PUPDR             (PIN_PUPDR_PULLUP(GPIOA_PIN0) |       \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN1) |       \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN2) |     \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN3) |     \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN4) |       \
+                                     PIN_PUPDR_PULLUP(GPIOA_SCK) |  \
+                                     PIN_PUPDR_PULLUP(GPIOA_MISO) |      \
+                                     PIN_PUPDR_PULLUP(GPIOA_MOSI) |      \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN8) |       \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN9) |       \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN10) |       \
+                                     PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DM) |  \
+                                     PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DP) |  \
+                                     PIN_PUPDR_PULLUP(GPIOA_SWDIO) |        \
+                                     PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) |      \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN15))
+#define VAL_GPIOA_ODR               (PIN_ODR_HIGH(GPIOA_PIN0) |           \
+                                     PIN_ODR_HIGH(GPIOA_PIN1) |           \
+                                     PIN_ODR_HIGH(GPIOA_PIN2) |           \
+                                     PIN_ODR_HIGH(GPIOA_PIN3) |           \
+                                     PIN_ODR_HIGH(GPIOA_PIN4) |           \
+                                     PIN_ODR_HIGH(GPIOA_SCK) |         \
+                                     PIN_ODR_HIGH(GPIOA_MISO) |          \
+                                     PIN_ODR_HIGH(GPIOA_MOSI) |          \
+                                     PIN_ODR_HIGH(GPIOA_PIN8) |           \
+                                     PIN_ODR_HIGH(GPIOA_PIN9) |           \
+                                     PIN_ODR_HIGH(GPIOA_PIN10) |           \
+                                     PIN_ODR_HIGH(GPIOA_OTG_FS_DM) |        \
+                                     PIN_ODR_HIGH(GPIOA_OTG_FS_DP) |        \
+                                     PIN_ODR_HIGH(GPIOA_SWDIO) |            \
+                                     PIN_ODR_HIGH(GPIOA_SWCLK) |            \
+                                     PIN_ODR_HIGH(GPIOA_PIN15))
+#define VAL_GPIOA_AFRL              (PIN_AFIO_AF(GPIOA_PIN0, 0U) |        \
+                                     PIN_AFIO_AF(GPIOA_PIN1, 0U) |        \
+                                     PIN_AFIO_AF(GPIOA_PIN2, 0U) |        \
+                                     PIN_AFIO_AF(GPIOA_PIN3, 0U) |        \
+                                     PIN_AFIO_AF(GPIOA_PIN4, 0U) |        \
+                                     PIN_AFIO_AF(GPIOA_SCK, 5U) |     \
+                                     PIN_AFIO_AF(GPIOA_MISO, 5U) |       \
+                                     PIN_AFIO_AF(GPIOA_MOSI, 5U))
+#define VAL_GPIOA_AFRH              (PIN_AFIO_AF(GPIOA_PIN8, 0U) |        \
+                                     PIN_AFIO_AF(GPIOA_PIN9, 0U) |        \
+                                     PIN_AFIO_AF(GPIOA_PIN10, 0U) |        \
+                                     PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10U) |    \
+                                     PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10U) |    \
+                                     PIN_AFIO_AF(GPIOA_SWDIO, 0U) |         \
+                                     PIN_AFIO_AF(GPIOA_SWCLK, 0U) |         \
+                                     PIN_AFIO_AF(GPIOA_PIN15, 0U))
+
+/*
+ * GPIOB setup:
+ *
+ * PB0  -                           (input pullup).
+ * PB1  -                           (input pullup).
+ * PB2  -                           (input pullup).
+ * PB3  - SWO                       (alternate 0).
+ * PB4  -                           (input pullup).
+ * PB5  -                           (input pullup).
+ * PB6  -                           (input pullup).
+ * PB7  -                           (input pullup).
+ * PB8  -                           (input pullup).
+ * PB9  -                           (input pullup).
+ * PB10 -                           (input pullup).
+ * PB11 -                           (input pullup).
+ * PB12 -                           (input pullup).
+ * PB13 -                           (input pullup).
+ * PB14 -                           (input pullup).
+ * PB15 -                           (input pullup).
+ */
+#define VAL_GPIOB_MODER             (PIN_MODE_INPUT(GPIOB_PIN0) |         \
+                                     PIN_MODE_INPUT(GPIOB_PIN1) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN2) |           \
+                                     PIN_MODE_ALTERNATE(GPIOB_SWO) |        \
+                                     PIN_MODE_INPUT(GPIOB_PIN4) |         \
+                                     PIN_MODE_INPUT(GPIOB_PIN5) |         \
+                                     PIN_MODE_INPUT(GPIOB_PIN6) |        \
+                                     PIN_MODE_INPUT(GPIOB_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN8) |        \
+                                     PIN_MODE_INPUT(GPIOB_PIN9) |        \
+                                     PIN_MODE_INPUT(GPIOB_PIN10) |         \
+                                     PIN_MODE_INPUT(GPIOB_PIN11) |          \
+                                     PIN_MODE_INPUT(GPIOB_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOB_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOB_PIN14) |          \
+                                     PIN_MODE_INPUT(GPIOB_PIN15))
+#define VAL_GPIOB_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_SWO) |        \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN4) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN5) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN6) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN8) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN9) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN10) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN14) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN15))
+#define VAL_GPIOB_OSPEEDR           (PIN_OSPEED_VERYLOW(GPIOB_PIN0) |        \
+                                     PIN_OSPEED_VERYLOW(GPIOB_PIN1) |          \
+                                     PIN_OSPEED_VERYLOW(GPIOB_PIN2) |          \
+                                     PIN_OSPEED_HIGH(GPIOB_SWO) |           \
+                                     PIN_OSPEED_VERYLOW(GPIOB_PIN4) |        \
+                                     PIN_OSPEED_VERYLOW(GPIOB_PIN5) |        \
+                                     PIN_OSPEED_VERYLOW(GPIOB_PIN6) |       \
+                                     PIN_OSPEED_VERYLOW(GPIOB_PIN7) |          \
+                                     PIN_OSPEED_VERYLOW(GPIOB_PIN8) |       \
+                                     PIN_OSPEED_VERYLOW(GPIOB_PIN9) |       \
+                                     PIN_OSPEED_VERYLOW(GPIOB_PIN10) |        \
+                                     PIN_OSPEED_VERYLOW(GPIOB_PIN11) |         \
+                                     PIN_OSPEED_VERYLOW(GPIOB_PIN12) |         \
+                                     PIN_OSPEED_VERYLOW(GPIOB_PIN13) |         \
+                                     PIN_OSPEED_VERYLOW(GPIOB_PIN14) |         \
+                                     PIN_OSPEED_VERYLOW(GPIOB_PIN15))
+#define VAL_GPIOB_PUPDR             (PIN_PUPDR_PULLUP(GPIOB_PIN0) |       \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN1) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN2) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_SWO) |          \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN4) |       \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN5) |       \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN6) |      \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN7) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN8) |      \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN9) |      \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN10) |       \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN11) |        \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN12) |        \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN13) |        \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN14) |        \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN15))
+#define VAL_GPIOB_ODR               (PIN_ODR_HIGH(GPIOB_PIN0) |           \
+                                     PIN_ODR_HIGH(GPIOB_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOB_SWO) |              \
+                                     PIN_ODR_HIGH(GPIOB_PIN4) |           \
+                                     PIN_ODR_HIGH(GPIOB_PIN5) |           \
+                                     PIN_ODR_HIGH(GPIOB_PIN6) |          \
+                                     PIN_ODR_HIGH(GPIOB_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN8) |          \
+                                     PIN_ODR_HIGH(GPIOB_PIN9) |          \
+                                     PIN_ODR_HIGH(GPIOB_PIN10) |           \
+                                     PIN_ODR_HIGH(GPIOB_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOB_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOB_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOB_PIN14) |            \
+                                     PIN_ODR_HIGH(GPIOB_PIN15))
+#define VAL_GPIOB_AFRL              (PIN_AFIO_AF(GPIOB_PIN0, 0U) |        \
+                                     PIN_AFIO_AF(GPIOB_PIN1, 0U) |          \
+                                     PIN_AFIO_AF(GPIOB_PIN2, 0U) |          \
+                                     PIN_AFIO_AF(GPIOB_SWO, 0U) |           \
+                                     PIN_AFIO_AF(GPIOB_PIN4, 0U) |        \
+                                     PIN_AFIO_AF(GPIOB_PIN5, 0U) |        \
+                                     PIN_AFIO_AF(GPIOB_PIN6, 0U) |       \
+                                     PIN_AFIO_AF(GPIOB_PIN7, 0U))
+#define VAL_GPIOB_AFRH              (PIN_AFIO_AF(GPIOB_PIN8, 0U) |       \
+                                     PIN_AFIO_AF(GPIOB_PIN9, 0U) |       \
+                                     PIN_AFIO_AF(GPIOB_PIN10, 0U) |        \
+                                     PIN_AFIO_AF(GPIOB_PIN11, 0U) |         \
+                                     PIN_AFIO_AF(GPIOB_PIN12, 0U) |         \
+                                     PIN_AFIO_AF(GPIOB_PIN13, 0U) |         \
+                                     PIN_AFIO_AF(GPIOB_PIN14, 0U) |         \
+                                     PIN_AFIO_AF(GPIOB_PIN15, 0U))
+
+/*
+ * GPIOC setup:
+ *
+ * PC0  -                           (input pullup).
+ * PC1  -                           (input pullup).
+ * PC2  -                           (input pullup).
+ * PC3  -                           (input pullup).
+ * PC4  -                           (input pullup).
+ * PC5  -                           (input pullup).
+ * PC6  -                           (input pullup).
+ * PC7  -                           (input pullup).
+ * PC8  -                           (input pullup).
+ * PC9  -                           (input pullup).
+ * PC10 -                           (input pullup).
+ * PC11 -                           (input pullup).
+ * PC12 -                           (input pullup).
+ * PC13 -                           (input floating).
+ * PC14 -                           (input floating).
+ * PC15 -                           (input floating).
+ */
+#define VAL_GPIOC_MODER             (PIN_MODE_INPUT(GPIOC_PIN0) |         \
+                                     PIN_MODE_INPUT(GPIOC_PIN1) |         \
+                                     PIN_MODE_INPUT(GPIOC_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN7) |         \
+                                     PIN_MODE_INPUT(GPIOC_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN9) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOC_PIN11) |          \
+                                     PIN_MODE_INPUT(GPIOC_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOC_PIN13) |         \
+                                     PIN_MODE_INPUT(GPIOC_PIN14) |       \
+                                     PIN_MODE_INPUT(GPIOC_PIN15))
+#define VAL_GPIOC_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN1) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN7) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN13) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN14) |   \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN15))
+#define VAL_GPIOC_OSPEEDR           (PIN_OSPEED_VERYLOW(GPIOC_PIN0) |        \
+                                     PIN_OSPEED_VERYLOW(GPIOC_PIN1) |        \
+                                     PIN_OSPEED_VERYLOW(GPIOC_PIN2) |          \
+                                     PIN_OSPEED_VERYLOW(GPIOC_PIN3) |          \
+                                     PIN_OSPEED_VERYLOW(GPIOC_PIN4) |          \
+                                     PIN_OSPEED_VERYLOW(GPIOC_PIN5) |          \
+                                     PIN_OSPEED_VERYLOW(GPIOC_PIN6) |          \
+                                     PIN_OSPEED_VERYLOW(GPIOC_PIN7) |        \
+                                     PIN_OSPEED_VERYLOW(GPIOC_PIN8) |          \
+                                     PIN_OSPEED_VERYLOW(GPIOC_PIN9) |          \
+                                     PIN_OSPEED_VERYLOW(GPIOC_PIN10) |         \
+                                     PIN_OSPEED_VERYLOW(GPIOC_PIN11) |         \
+