From b624f32f944acdc59dcb130674c09090c5c404cb Mon Sep 17 00:00:00 2001 From: skullY Date: Fri, 30 Aug 2019 11:19:03 -0700 Subject: clang-format changes --- tmk_core/protocol/adb.c | 171 +-- tmk_core/protocol/adb.h | 13 +- tmk_core/protocol/arm_atsam/adc.c | 110 +- tmk_core/protocol/arm_atsam/adc.h | 10 +- tmk_core/protocol/arm_atsam/arm_atsam_protocol.h | 27 +- tmk_core/protocol/arm_atsam/clks.c | 375 ++--- tmk_core/protocol/arm_atsam/clks.h | 56 +- tmk_core/protocol/arm_atsam/d51_util.c | 289 ++-- tmk_core/protocol/arm_atsam/d51_util.h | 73 +- tmk_core/protocol/arm_atsam/i2c_master.c | 526 ++++--- tmk_core/protocol/arm_atsam/i2c_master.h | 130 +- tmk_core/protocol/arm_atsam/issi3733_driver.h | 260 ++-- tmk_core/protocol/arm_atsam/led_matrix.c | 430 +++--- tmk_core/protocol/arm_atsam/led_matrix.h | 146 +- tmk_core/protocol/arm_atsam/led_matrix_programs.c | 108 +- tmk_core/protocol/arm_atsam/main_arm_atsam.c | 185 ++- tmk_core/protocol/arm_atsam/main_arm_atsam.h | 2 +- tmk_core/protocol/arm_atsam/md_bootloader.h | 16 +- tmk_core/protocol/arm_atsam/spi.c | 83 +- tmk_core/protocol/arm_atsam/spi.h | 48 +- tmk_core/protocol/arm_atsam/startup.c | 776 +++++------ tmk_core/protocol/arm_atsam/usb/compiler.h | 934 ++++++------- tmk_core/protocol/arm_atsam/usb/conf_usb.h | 73 +- tmk_core/protocol/arm_atsam/usb/main_usb.c | 74 +- tmk_core/protocol/arm_atsam/usb/status_codes.h | 98 +- tmk_core/protocol/arm_atsam/usb/udc.c | 651 ++++----- tmk_core/protocol/arm_atsam/usb/udc.h | 26 +- tmk_core/protocol/arm_atsam/usb/udc_desc.h | 29 +- tmk_core/protocol/arm_atsam/usb/udd.h | 40 +- tmk_core/protocol/arm_atsam/usb/udi.h | 96 +- tmk_core/protocol/arm_atsam/usb/udi_cdc.c | 857 +++++------- tmk_core/protocol/arm_atsam/usb/udi_cdc.h | 58 +- tmk_core/protocol/arm_atsam/usb/udi_cdc_conf.h | 16 +- tmk_core/protocol/arm_atsam/usb/udi_device_conf.h | 654 +++------ .../protocol/arm_atsam/usb/udi_device_epsize.h | 21 +- tmk_core/protocol/arm_atsam/usb/udi_hid.c | 82 +- tmk_core/protocol/arm_atsam/usb/udi_hid.h | 4 +- tmk_core/protocol/arm_atsam/usb/udi_hid_kbd.c | 789 +++++------ tmk_core/protocol/arm_atsam/usb/udi_hid_kbd.h | 48 +- tmk_core/protocol/arm_atsam/usb/udi_hid_kbd_conf.h | 2 +- tmk_core/protocol/arm_atsam/usb/udi_hid_kbd_desc.c | 108 +- tmk_core/protocol/arm_atsam/usb/ui.c | 39 +- tmk_core/protocol/arm_atsam/usb/ui.h | 2 +- tmk_core/protocol/arm_atsam/usb/usb.c | 345 ++--- tmk_core/protocol/arm_atsam/usb/usb.h | 110 +- tmk_core/protocol/arm_atsam/usb/usb2422.c | 366 ++--- tmk_core/protocol/arm_atsam/usb/usb2422.h | 384 +++-- tmk_core/protocol/arm_atsam/usb/usb_atmel.h | 181 ++- tmk_core/protocol/arm_atsam/usb/usb_device_udd.c | 386 +++--- tmk_core/protocol/arm_atsam/usb/usb_main.h | 51 +- tmk_core/protocol/arm_atsam/usb/usb_protocol.h | 252 ++-- tmk_core/protocol/arm_atsam/usb/usb_protocol_cdc.h | 215 ++- tmk_core/protocol/arm_atsam/usb/usb_protocol_hid.h | 383 +++-- tmk_core/protocol/arm_atsam/usb/usb_util.c | 54 +- tmk_core/protocol/arm_atsam/usb/usb_util.h | 3 +- tmk_core/protocol/arm_atsam/wait_api.h | 1 - tmk_core/protocol/bluefruit/bluefruit.c | 123 +- tmk_core/protocol/bluefruit/bluefruit.h | 1 - tmk_core/protocol/bluefruit/main.c | 91 +- .../chibios/lufa_utils/LUFA/Drivers/USB/USB.h | 8 +- tmk_core/protocol/chibios/main.c | 180 ++- tmk_core/protocol/chibios/usb_driver.c | 435 +++--- tmk_core/protocol/chibios/usb_driver.h | 168 ++- tmk_core/protocol/chibios/usb_main.c | 1048 +++++++------- tmk_core/protocol/chibios/usb_main.h | 7 +- tmk_core/protocol/ibm4704.c | 62 +- tmk_core/protocol/ibm4704.h | 113 +- tmk_core/protocol/iwrap/iwrap.c | 202 +-- tmk_core/protocol/iwrap/iwrap.h | 16 +- tmk_core/protocol/iwrap/main.c | 312 +++-- tmk_core/protocol/iwrap/suart.h | 4 +- tmk_core/protocol/iwrap/wd.h | 134 +- tmk_core/protocol/lufa/adafruit_ble.cpp | 1117 ++++++++------- tmk_core/protocol/lufa/adafruit_ble.h | 30 +- tmk_core/protocol/lufa/bluetooth.c | 20 +- tmk_core/protocol/lufa/bluetooth.h | 37 +- tmk_core/protocol/lufa/lufa.c | 692 ++++----- tmk_core/protocol/lufa/lufa.h | 20 +- tmk_core/protocol/lufa/outputselect.c | 9 +- tmk_core/protocol/lufa/outputselect.h | 14 +- tmk_core/protocol/m0110.c | 262 ++-- tmk_core/protocol/m0110.h | 48 +- tmk_core/protocol/mbed/HIDKeyboard.cpp | 241 ++-- tmk_core/protocol/mbed/HIDKeyboard.h | 37 +- tmk_core/protocol/mbed/mbed_driver.cpp | 40 +- tmk_core/protocol/midi/Config/LUFAConfig.h | 28 +- tmk_core/protocol/midi/bytequeue/bytequeue.c | 93 +- tmk_core/protocol/midi/bytequeue/bytequeue.h | 59 +- .../protocol/midi/bytequeue/interrupt_setting.c | 54 +- .../protocol/midi/bytequeue/interrupt_setting.h | 33 +- tmk_core/protocol/midi/midi.c | 344 ++--- tmk_core/protocol/midi/midi.h | 152 +- tmk_core/protocol/midi/midi_device.c | 477 +++---- tmk_core/protocol/midi/midi_device.h | 121 +- tmk_core/protocol/midi/midi_function_types.h | 44 +- tmk_core/protocol/midi/qmk_midi.c | 258 ++-- tmk_core/protocol/midi/qmk_midi.h | 10 +- tmk_core/protocol/midi/sysex_tools.c | 158 ++- tmk_core/protocol/midi/sysex_tools.h | 34 +- tmk_core/protocol/news.c | 19 +- tmk_core/protocol/news.h | 3 +- tmk_core/protocol/next_kbd.c | 127 +- tmk_core/protocol/next_kbd.h | 12 +- tmk_core/protocol/pjrc/main.c | 18 +- tmk_core/protocol/pjrc/pjrc.c | 40 +- tmk_core/protocol/pjrc/pjrc.h | 1 - tmk_core/protocol/pjrc/usb.c | 1464 ++++++++++---------- tmk_core/protocol/pjrc/usb.h | 144 +- tmk_core/protocol/pjrc/usb_debug.c | 128 +- tmk_core/protocol/pjrc/usb_debug.h | 15 +- tmk_core/protocol/pjrc/usb_extra.c | 70 +- tmk_core/protocol/pjrc/usb_extra.h | 12 +- tmk_core/protocol/pjrc/usb_keyboard.c | 62 +- tmk_core/protocol/pjrc/usb_keyboard.h | 8 +- tmk_core/protocol/pjrc/usb_mouse.c | 88 +- tmk_core/protocol/pjrc/usb_mouse.h | 25 +- tmk_core/protocol/ps2.h | 70 +- tmk_core/protocol/ps2_busywait.c | 60 +- tmk_core/protocol/ps2_interrupt.c | 112 +- tmk_core/protocol/ps2_io.h | 1 - tmk_core/protocol/ps2_io_avr.c | 69 +- tmk_core/protocol/ps2_io_mbed.c | 29 +- tmk_core/protocol/ps2_mouse.c | 102 +- tmk_core/protocol/ps2_mouse.h | 163 ++- tmk_core/protocol/ps2_usart.c | 88 +- tmk_core/protocol/serial.h | 4 +- tmk_core/protocol/serial_mouse.h | 3 +- tmk_core/protocol/serial_mouse_microsoft.c | 35 +- tmk_core/protocol/serial_mouse_mousesystems.c | 38 +- tmk_core/protocol/serial_soft.c | 81 +- tmk_core/protocol/serial_uart.c | 58 +- tmk_core/protocol/usb_descriptor.c | 1072 +++++--------- tmk_core/protocol/usb_descriptor.h | 250 ++-- tmk_core/protocol/vusb/main.c | 42 +- tmk_core/protocol/vusb/sendchar_usart.c | 12 +- tmk_core/protocol/vusb/usbdrv/oddebug.c | 22 +- tmk_core/protocol/vusb/usbdrv/oddebug.h | 114 +- .../protocol/vusb/usbdrv/usbconfig-prototype.h | 86 +- tmk_core/protocol/vusb/usbdrv/usbdrv.c | 673 +++++---- tmk_core/protocol/vusb/usbdrv/usbdrv.h | 487 ++++--- tmk_core/protocol/vusb/vusb.c | 498 +++---- tmk_core/protocol/vusb/vusb.h | 3 +- tmk_core/protocol/xt.h | 56 +- tmk_core/protocol/xt_interrupt.c | 54 +- 144 files changed, 11452 insertions(+), 13668 deletions(-) mode change 100755 => 100644 tmk_core/protocol/midi/Config/LUFAConfig.h mode change 100755 => 100644 tmk_core/protocol/midi/bytequeue/bytequeue.c mode change 100755 => 100644 tmk_core/protocol/midi/bytequeue/bytequeue.h mode change 100755 => 100644 tmk_core/protocol/midi/bytequeue/interrupt_setting.c mode change 100755 => 100644 tmk_core/protocol/midi/bytequeue/interrupt_setting.h mode change 100755 => 100644 tmk_core/protocol/midi/midi.c mode change 100755 => 100644 tmk_core/protocol/midi/midi.h mode change 100755 => 100644 tmk_core/protocol/midi/midi_device.c mode change 100755 => 100644 tmk_core/protocol/midi/midi_device.h mode change 100755 => 100644 tmk_core/protocol/midi/midi_function_types.h mode change 100755 => 100644 tmk_core/protocol/midi/sysex_tools.c mode change 100755 => 100644 tmk_core/protocol/midi/sysex_tools.h (limited to 'tmk_core/protocol') diff --git a/tmk_core/protocol/adb.c b/tmk_core/protocol/adb.c index 5c6c99b4fc..a23c919619 100644 --- a/tmk_core/protocol/adb.c +++ b/tmk_core/protocol/adb.c @@ -42,11 +42,10 @@ POSSIBILITY OF SUCH DAMAGE. #include #include "adb.h" - // GCC doesn't inline functions normally -#define data_lo() (ADB_DDR |= (1<>i)) + if (data & (0x80 >> i)) place_bit1(); else place_bit0(); @@ -275,29 +243,22 @@ static inline void send_byte(uint8_t data) // These are carefully coded to take 6 cycles of overhead. // inline asm approach became too convoluted -static inline uint16_t wait_data_lo(uint16_t us) -{ +static inline uint16_t wait_data_lo(uint16_t us) { do { - if ( !data_in() ) - break; + if (!data_in()) break; _delay_us(1 - (6 * 1000000.0 / F_CPU)); - } - while ( --us ); + } while (--us); return us; } -static inline uint16_t wait_data_hi(uint16_t us) -{ +static inline uint16_t wait_data_hi(uint16_t us) { do { - if ( data_in() ) - break; + if (data_in()) break; _delay_us(1 - (6 * 1000000.0 / F_CPU)); - } - while ( --us ); + } while (--us); return us; } - /* ADB Protocol ============ @@ -375,7 +336,7 @@ Commands A A A A 1 1 R R Talk(read from a device) The command to read keycodes from keyboard is 0x2C which - consist of keyboard address 2 and Talk against register 0. + consist of keyboard address 2 and Talk against register 0. Address: 2: keyboard @@ -457,7 +418,7 @@ Keyboard Data(Register0) Keyboard LEDs & state of keys(Register2) This register hold current state of three LEDs and nine keys. The state of LEDs can be changed by sending Listen command. - + 1514 . . . . . . 7 6 5 . 3 2 1 0 | | | | | | | | | | | | | | | +- LED1(NumLock) | | | | | | | | | | | | | | +--- LED2(CapsLock) diff --git a/tmk_core/protocol/adb.h b/tmk_core/protocol/adb.h index b4b3633cf4..7d37485fcd 100644 --- a/tmk_core/protocol/adb.h +++ b/tmk_core/protocol/adb.h @@ -41,16 +41,12 @@ POSSIBILITY OF SUCH DAMAGE. #include #include -#if !(defined(ADB_PORT) && \ - defined(ADB_PIN) && \ - defined(ADB_DDR) && \ - defined(ADB_DATA_BIT)) -# error "ADB port setting is required in config.h" +#if !(defined(ADB_PORT) && defined(ADB_PIN) && defined(ADB_DDR) && defined(ADB_DATA_BIT)) +# error "ADB port setting is required in config.h" #endif -#define ADB_POWER 0x7F -#define ADB_CAPS 0x39 - +#define ADB_POWER 0x7F +#define ADB_CAPS 0x39 // ADB host void adb_host_init(void); @@ -62,5 +58,4 @@ void adb_host_kbd_led(uint8_t led); void adb_mouse_task(void); void adb_mouse_init(void); - #endif diff --git a/tmk_core/protocol/arm_atsam/adc.c b/tmk_core/protocol/arm_atsam/adc.c index cb5c349b73..1ef1b11d57 100644 --- a/tmk_core/protocol/arm_atsam/adc.c +++ b/tmk_core/protocol/arm_atsam/adc.c @@ -24,76 +24,92 @@ uint16_t v_con_2; uint16_t v_con_1_boot; uint16_t v_con_2_boot; -void ADC0_clock_init(void) -{ +void ADC0_clock_init(void) { DBGC(DC_ADC0_CLOCK_INIT_BEGIN); - MCLK->APBDMASK.bit.ADC0_ = 1; //ADC0 Clock Enable + MCLK->APBDMASK.bit.ADC0_ = 1; // ADC0 Clock Enable - GCLK->PCHCTRL[ADC0_GCLK_ID].bit.GEN = GEN_OSC0; //Select generator clock - GCLK->PCHCTRL[ADC0_GCLK_ID].bit.CHEN = 1; //Enable peripheral clock + GCLK->PCHCTRL[ADC0_GCLK_ID].bit.GEN = GEN_OSC0; // Select generator clock + GCLK->PCHCTRL[ADC0_GCLK_ID].bit.CHEN = 1; // Enable peripheral clock DBGC(DC_ADC0_CLOCK_INIT_COMPLETE); } -void ADC0_init(void) -{ +void ADC0_init(void) { DBGC(DC_ADC0_INIT_BEGIN); - //MCU - PORT->Group[1].DIRCLR.reg = 1 << 0; //PB00 as input 5V - PORT->Group[1].DIRCLR.reg = 1 << 1; //PB01 as input CON2 - PORT->Group[1].DIRCLR.reg = 1 << 2; //PB02 as input CON1 - PORT->Group[1].PMUX[0].bit.PMUXE = 1; //PB00 mux select B ADC 5V - PORT->Group[1].PMUX[0].bit.PMUXO = 1; //PB01 mux select B ADC CON2 - PORT->Group[1].PMUX[1].bit.PMUXE = 1; //PB02 mux select B ADC CON1 - PORT->Group[1].PINCFG[0].bit.PMUXEN = 1; //PB01 mux ADC Enable 5V - PORT->Group[1].PINCFG[1].bit.PMUXEN = 1; //PB01 mux ADC Enable CON2 - PORT->Group[1].PINCFG[2].bit.PMUXEN = 1; //PB02 mux ADC Enable CON1 - - //ADC + // MCU + PORT->Group[1].DIRCLR.reg = 1 << 0; // PB00 as input 5V + PORT->Group[1].DIRCLR.reg = 1 << 1; // PB01 as input CON2 + PORT->Group[1].DIRCLR.reg = 1 << 2; // PB02 as input CON1 + PORT->Group[1].PMUX[0].bit.PMUXE = 1; // PB00 mux select B ADC 5V + PORT->Group[1].PMUX[0].bit.PMUXO = 1; // PB01 mux select B ADC CON2 + PORT->Group[1].PMUX[1].bit.PMUXE = 1; // PB02 mux select B ADC CON1 + PORT->Group[1].PINCFG[0].bit.PMUXEN = 1; // PB01 mux ADC Enable 5V + PORT->Group[1].PINCFG[1].bit.PMUXEN = 1; // PB01 mux ADC Enable CON2 + PORT->Group[1].PINCFG[2].bit.PMUXEN = 1; // PB02 mux ADC Enable CON1 + + // ADC ADC0->CTRLA.bit.SWRST = 1; - while (ADC0->SYNCBUSY.bit.SWRST) { DBGC(DC_ADC0_SWRST_SYNCING_1); } - while (ADC0->CTRLA.bit.SWRST) { DBGC(DC_ADC0_SWRST_SYNCING_2); } - - //Clock divide + while (ADC0->SYNCBUSY.bit.SWRST) { + DBGC(DC_ADC0_SWRST_SYNCING_1); + } + while (ADC0->CTRLA.bit.SWRST) { + DBGC(DC_ADC0_SWRST_SYNCING_2); + } + + // Clock divide ADC0->CTRLA.bit.PRESCALER = ADC_CTRLA_PRESCALER_DIV2_Val; - //Averaging + // Averaging ADC0->AVGCTRL.bit.SAMPLENUM = ADC_AVGCTRL_SAMPLENUM_4_Val; - while (ADC0->SYNCBUSY.bit.AVGCTRL) { DBGC(DC_ADC0_AVGCTRL_SYNCING_1); } - if (ADC0->AVGCTRL.bit.SAMPLENUM == ADC_AVGCTRL_SAMPLENUM_1_Val) ADC0->AVGCTRL.bit.ADJRES = 0; - else if (ADC0->AVGCTRL.bit.SAMPLENUM == ADC_AVGCTRL_SAMPLENUM_2_Val) ADC0->AVGCTRL.bit.ADJRES = 1; - else if (ADC0->AVGCTRL.bit.SAMPLENUM == ADC_AVGCTRL_SAMPLENUM_4_Val) ADC0->AVGCTRL.bit.ADJRES = 2; - else if (ADC0->AVGCTRL.bit.SAMPLENUM == ADC_AVGCTRL_SAMPLENUM_8_Val) ADC0->AVGCTRL.bit.ADJRES = 3; - else ADC0->AVGCTRL.bit.ADJRES = 4; - while (ADC0->SYNCBUSY.bit.AVGCTRL) { DBGC(DC_ADC0_AVGCTRL_SYNCING_2); } - - //Settling - ADC0->SAMPCTRL.bit.SAMPLEN = 45; //Sampling Time Length: 1-63, 1 ADC CLK per - while (ADC0->SYNCBUSY.bit.SAMPCTRL) { DBGC(DC_ADC0_SAMPCTRL_SYNCING_1); } - - //Load factory calibration data - ADC0->CALIB.bit.BIASCOMP = ((*(uint32_t *)ADC0_FUSES_BIASCOMP_ADDR) & ADC0_FUSES_BIASCOMP_Msk) >> ADC0_FUSES_BIASCOMP_Pos; - ADC0->CALIB.bit.BIASR2R = ((*(uint32_t *)ADC0_FUSES_BIASR2R_ADDR) & ADC0_FUSES_BIASR2R_Msk) >> ADC0_FUSES_BIASR2R_Pos; + while (ADC0->SYNCBUSY.bit.AVGCTRL) { + DBGC(DC_ADC0_AVGCTRL_SYNCING_1); + } + if (ADC0->AVGCTRL.bit.SAMPLENUM == ADC_AVGCTRL_SAMPLENUM_1_Val) + ADC0->AVGCTRL.bit.ADJRES = 0; + else if (ADC0->AVGCTRL.bit.SAMPLENUM == ADC_AVGCTRL_SAMPLENUM_2_Val) + ADC0->AVGCTRL.bit.ADJRES = 1; + else if (ADC0->AVGCTRL.bit.SAMPLENUM == ADC_AVGCTRL_SAMPLENUM_4_Val) + ADC0->AVGCTRL.bit.ADJRES = 2; + else if (ADC0->AVGCTRL.bit.SAMPLENUM == ADC_AVGCTRL_SAMPLENUM_8_Val) + ADC0->AVGCTRL.bit.ADJRES = 3; + else + ADC0->AVGCTRL.bit.ADJRES = 4; + while (ADC0->SYNCBUSY.bit.AVGCTRL) { + DBGC(DC_ADC0_AVGCTRL_SYNCING_2); + } + + // Settling + ADC0->SAMPCTRL.bit.SAMPLEN = 45; // Sampling Time Length: 1-63, 1 ADC CLK per + while (ADC0->SYNCBUSY.bit.SAMPCTRL) { + DBGC(DC_ADC0_SAMPCTRL_SYNCING_1); + } + + // Load factory calibration data + ADC0->CALIB.bit.BIASCOMP = ((*(uint32_t *)ADC0_FUSES_BIASCOMP_ADDR) & ADC0_FUSES_BIASCOMP_Msk) >> ADC0_FUSES_BIASCOMP_Pos; + ADC0->CALIB.bit.BIASR2R = ((*(uint32_t *)ADC0_FUSES_BIASR2R_ADDR) & ADC0_FUSES_BIASR2R_Msk) >> ADC0_FUSES_BIASR2R_Pos; ADC0->CALIB.bit.BIASREFBUF = ((*(uint32_t *)ADC0_FUSES_BIASREFBUF_ADDR) & ADC0_FUSES_BIASREFBUF_Msk) >> ADC0_FUSES_BIASREFBUF_Pos; - //Enable + // Enable ADC0->CTRLA.bit.ENABLE = 1; - while (ADC0->SYNCBUSY.bit.ENABLE) { DBGC(DC_ADC0_ENABLE_SYNCING_1); } + while (ADC0->SYNCBUSY.bit.ENABLE) { + DBGC(DC_ADC0_ENABLE_SYNCING_1); + } DBGC(DC_ADC0_INIT_COMPLETE); } -uint16_t adc_get(uint8_t muxpos) -{ +uint16_t adc_get(uint8_t muxpos) { ADC0->INPUTCTRL.bit.MUXPOS = muxpos; - while (ADC0->SYNCBUSY.bit.INPUTCTRL) {} + while (ADC0->SYNCBUSY.bit.INPUTCTRL) { + } ADC0->SWTRIG.bit.START = 1; - while (ADC0->SYNCBUSY.bit.SWTRIG) {} - while (!ADC0->INTFLAG.bit.RESRDY) {} + while (ADC0->SYNCBUSY.bit.SWTRIG) { + } + while (!ADC0->INTFLAG.bit.RESRDY) { + } return ADC0->RESULT.reg; } - diff --git a/tmk_core/protocol/arm_atsam/adc.h b/tmk_core/protocol/arm_atsam/adc.h index 5a90ece3fe..9ab653e5a2 100644 --- a/tmk_core/protocol/arm_atsam/adc.h +++ b/tmk_core/protocol/arm_atsam/adc.h @@ -18,11 +18,11 @@ along with this program. If not, see . #ifndef _ADC_H_ #define _ADC_H_ -#define ADC_5V_START_LEVEL 2365 +#define ADC_5V_START_LEVEL 2365 -#define ADC_5V ADC_INPUTCTRL_MUXPOS_AIN12_Val -#define ADC_CON1 ADC_INPUTCTRL_MUXPOS_AIN14_Val -#define ADC_CON2 ADC_INPUTCTRL_MUXPOS_AIN13_Val +#define ADC_5V ADC_INPUTCTRL_MUXPOS_AIN12_Val +#define ADC_CON1 ADC_INPUTCTRL_MUXPOS_AIN14_Val +#define ADC_CON2 ADC_INPUTCTRL_MUXPOS_AIN13_Val extern uint16_t v_5v; extern uint16_t v_5v_avg; @@ -34,4 +34,4 @@ extern uint16_t v_con_2_boot; void ADC0_clock_init(void); void ADC0_init(void); -#endif //_ADC_H_ +#endif //_ADC_H_ diff --git a/tmk_core/protocol/arm_atsam/arm_atsam_protocol.h b/tmk_core/protocol/arm_atsam/arm_atsam_protocol.h index 88109186aa..8cb00b872a 100644 --- a/tmk_core/protocol/arm_atsam/arm_atsam_protocol.h +++ b/tmk_core/protocol/arm_atsam/arm_atsam_protocol.h @@ -33,17 +33,16 @@ along with this program. If not, see . #ifndef MD_BOOTLOADER -#include "main_arm_atsam.h" -#ifdef RGB_MATRIX_ENABLE -#include "led_matrix.h" -#include "rgb_matrix.h" -#endif -#include "issi3733_driver.h" -#include "./usb/compiler.h" -#include "./usb/udc.h" -#include "./usb/udi_cdc.h" - -#endif //MD_BOOTLOADER - -#endif //_ARM_ATSAM_PROTOCOL_H_ - +# include "main_arm_atsam.h" +# ifdef RGB_MATRIX_ENABLE +# include "led_matrix.h" +# include "rgb_matrix.h" +# endif +# include "issi3733_driver.h" +# include "./usb/compiler.h" +# include "./usb/udc.h" +# include "./usb/udi_cdc.h" + +#endif // MD_BOOTLOADER + +#endif //_ARM_ATSAM_PROTOCOL_H_ diff --git a/tmk_core/protocol/arm_atsam/clks.c b/tmk_core/protocol/arm_atsam/clks.c index 1ff318e59b..84ed6d83af 100644 --- a/tmk_core/protocol/arm_atsam/clks.c +++ b/tmk_core/protocol/arm_atsam/clks.c @@ -19,83 +19,105 @@ along with this program. If not, see . #include -volatile clk_t system_clks; +volatile clk_t system_clks; volatile uint64_t ms_clk; -uint32_t usec_delay_mult; -#define USEC_DELAY_LOOP_CYCLES 3 //Sum of instruction cycles in us delay loop +uint32_t usec_delay_mult; +#define USEC_DELAY_LOOP_CYCLES 3 // Sum of instruction cycles in us delay loop -const uint32_t sercom_apbbase[] = {(uint32_t)SERCOM0,(uint32_t)SERCOM1,(uint32_t)SERCOM2,(uint32_t)SERCOM3,(uint32_t)SERCOM4,(uint32_t)SERCOM5}; -const uint8_t sercom_pchan[] = {7, 8, 23, 24, 34, 35}; +const uint32_t sercom_apbbase[] = {(uint32_t)SERCOM0, (uint32_t)SERCOM1, (uint32_t)SERCOM2, (uint32_t)SERCOM3, (uint32_t)SERCOM4, (uint32_t)SERCOM5}; +const uint8_t sercom_pchan[] = {7, 8, 23, 24, 34, 35}; -#define USE_DPLL_IND 0 -#define USE_DPLL_DEF GCLK_SOURCE_DPLL0 +#define USE_DPLL_IND 0 +#define USE_DPLL_DEF GCLK_SOURCE_DPLL0 -void CLK_oscctrl_init(void) -{ +void CLK_oscctrl_init(void) { Oscctrl *posctrl = OSCCTRL; - Gclk *pgclk = GCLK; + Gclk * pgclk = GCLK; DBGC(DC_CLK_OSC_INIT_BEGIN); - //default setup on por - system_clks.freq_dfll = FREQ_DFLL_DEFAULT; + // default setup on por + system_clks.freq_dfll = FREQ_DFLL_DEFAULT; system_clks.freq_gclk[0] = system_clks.freq_dfll; - //configure and startup 16MHz xosc0 - posctrl->XOSCCTRL[0].bit.ENABLE = 0; - posctrl->XOSCCTRL[0].bit.STARTUP = 0xD; - posctrl->XOSCCTRL[0].bit.ENALC = 1; - posctrl->XOSCCTRL[0].bit.IMULT = 5; - posctrl->XOSCCTRL[0].bit.IPTAT = 3; + // configure and startup 16MHz xosc0 + posctrl->XOSCCTRL[0].bit.ENABLE = 0; + posctrl->XOSCCTRL[0].bit.STARTUP = 0xD; + posctrl->XOSCCTRL[0].bit.ENALC = 1; + posctrl->XOSCCTRL[0].bit.IMULT = 5; + posctrl->XOSCCTRL[0].bit.IPTAT = 3; posctrl->XOSCCTRL[0].bit.ONDEMAND = 0; - posctrl->XOSCCTRL[0].bit.XTALEN = 1; - posctrl->XOSCCTRL[0].bit.ENABLE = 1; - while (posctrl->STATUS.bit.XOSCRDY0 == 0) { DBGC(DC_CLK_OSC_INIT_XOSC0_SYNC); } + posctrl->XOSCCTRL[0].bit.XTALEN = 1; + posctrl->XOSCCTRL[0].bit.ENABLE = 1; + while (posctrl->STATUS.bit.XOSCRDY0 == 0) { + DBGC(DC_CLK_OSC_INIT_XOSC0_SYNC); + } system_clks.freq_xosc0 = FREQ_XOSC0; - //configure and startup DPLL + // configure and startup DPLL posctrl->Dpll[USE_DPLL_IND].DPLLCTRLA.bit.ENABLE = 0; - while (posctrl->Dpll[USE_DPLL_IND].DPLLSYNCBUSY.bit.ENABLE) { DBGC(DC_CLK_OSC_INIT_DPLL_SYNC_DISABLE); } - posctrl->Dpll[USE_DPLL_IND].DPLLCTRLB.bit.REFCLK = 2; //select XOSC0 (16MHz) - posctrl->Dpll[USE_DPLL_IND].DPLLCTRLB.bit.DIV = 7; //16 MHz / (2 * (7 + 1)) = 1 MHz - posctrl->Dpll[USE_DPLL_IND].DPLLRATIO.bit.LDR = PLL_RATIO; //1 MHz * (PLL_RATIO(47) + 1) = 48MHz - while (posctrl->Dpll[USE_DPLL_IND].DPLLSYNCBUSY.bit.DPLLRATIO) { DBGC(DC_CLK_OSC_INIT_DPLL_SYNC_RATIO); } + while (posctrl->Dpll[USE_DPLL_IND].DPLLSYNCBUSY.bit.ENABLE) { + DBGC(DC_CLK_OSC_INIT_DPLL_SYNC_DISABLE); + } + posctrl->Dpll[USE_DPLL_IND].DPLLCTRLB.bit.REFCLK = 2; // select XOSC0 (16MHz) + posctrl->Dpll[USE_DPLL_IND].DPLLCTRLB.bit.DIV = 7; // 16 MHz / (2 * (7 + 1)) = 1 MHz + posctrl->Dpll[USE_DPLL_IND].DPLLRATIO.bit.LDR = PLL_RATIO; // 1 MHz * (PLL_RATIO(47) + 1) = 48MHz + while (posctrl->Dpll[USE_DPLL_IND].DPLLSYNCBUSY.bit.DPLLRATIO) { + DBGC(DC_CLK_OSC_INIT_DPLL_SYNC_RATIO); + } posctrl->Dpll[USE_DPLL_IND].DPLLCTRLA.bit.ONDEMAND = 0; - posctrl->Dpll[USE_DPLL_IND].DPLLCTRLA.bit.ENABLE = 1; - while (posctrl->Dpll[USE_DPLL_IND].DPLLSYNCBUSY.bit.ENABLE) { DBGC(DC_CLK_OSC_INIT_DPLL_SYNC_ENABLE); } - while (posctrl->Dpll[USE_DPLL_IND].DPLLSTATUS.bit.LOCK == 0) { DBGC(DC_CLK_OSC_INIT_DPLL_WAIT_LOCK); } - while (posctrl->Dpll[USE_DPLL_IND].DPLLSTATUS.bit.CLKRDY == 0) { DBGC(DC_CLK_OSC_INIT_DPLL_WAIT_CLKRDY); } + posctrl->Dpll[USE_DPLL_IND].DPLLCTRLA.bit.ENABLE = 1; + while (posctrl->Dpll[USE_DPLL_IND].DPLLSYNCBUSY.bit.ENABLE) { + DBGC(DC_CLK_OSC_INIT_DPLL_SYNC_ENABLE); + } + while (posctrl->Dpll[USE_DPLL_IND].DPLLSTATUS.bit.LOCK == 0) { + DBGC(DC_CLK_OSC_INIT_DPLL_WAIT_LOCK); + } + while (posctrl->Dpll[USE_DPLL_IND].DPLLSTATUS.bit.CLKRDY == 0) { + DBGC(DC_CLK_OSC_INIT_DPLL_WAIT_CLKRDY); + } system_clks.freq_dpll[0] = (system_clks.freq_xosc0 / 2 / (posctrl->Dpll[USE_DPLL_IND].DPLLCTRLB.bit.DIV + 1)) * (posctrl->Dpll[USE_DPLL_IND].DPLLRATIO.bit.LDR + 1); - //change gclk0 to DPLL + // change gclk0 to DPLL pgclk->GENCTRL[GEN_DPLL0].bit.SRC = USE_DPLL_DEF; - while (pgclk->SYNCBUSY.bit.GENCTRL0) { DBGC(DC_CLK_OSC_INIT_GCLK_SYNC_GENCTRL0); } + while (pgclk->SYNCBUSY.bit.GENCTRL0) { + DBGC(DC_CLK_OSC_INIT_GCLK_SYNC_GENCTRL0); + } system_clks.freq_gclk[0] = system_clks.freq_dpll[0]; usec_delay_mult = system_clks.freq_gclk[0] / (USEC_DELAY_LOOP_CYCLES * 1000000); - if (usec_delay_mult < 1) usec_delay_mult = 1; //Never allow a multiplier of zero + if (usec_delay_mult < 1) usec_delay_mult = 1; // Never allow a multiplier of zero DBGC(DC_CLK_OSC_INIT_COMPLETE); } -//configure for 1MHz (1 usec timebase) -//call CLK_set_gclk_freq(GEN_TC45, FREQ_TC45_DEFAULT); -uint32_t CLK_set_gclk_freq(uint8_t gclkn, uint32_t freq) -{ +// configure for 1MHz (1 usec timebase) +// call CLK_set_gclk_freq(GEN_TC45, FREQ_TC45_DEFAULT); +uint32_t CLK_set_gclk_freq(uint8_t gclkn, uint32_t freq) { Gclk *pgclk = GCLK; DBGC(DC_CLK_SET_GCLK_FREQ_BEGIN); - while (pgclk->SYNCBUSY.vec.GENCTRL) { DBGC(DC_CLK_SET_GCLK_FREQ_SYNC_1); } + while (pgclk->SYNCBUSY.vec.GENCTRL) { + DBGC(DC_CLK_SET_GCLK_FREQ_SYNC_1); + } pgclk->GENCTRL[gclkn].bit.SRC = USE_DPLL_DEF; - while (pgclk->SYNCBUSY.vec.GENCTRL) { DBGC(DC_CLK_SET_GCLK_FREQ_SYNC_2); } + while (pgclk->SYNCBUSY.vec.GENCTRL) { + DBGC(DC_CLK_SET_GCLK_FREQ_SYNC_2); + } pgclk->GENCTRL[gclkn].bit.DIV = (uint8_t)(system_clks.freq_dpll[0] / freq); - while (pgclk->SYNCBUSY.vec.GENCTRL) { DBGC(DC_CLK_SET_GCLK_FREQ_SYNC_3); } + while (pgclk->SYNCBUSY.vec.GENCTRL) { + DBGC(DC_CLK_SET_GCLK_FREQ_SYNC_3); + } pgclk->GENCTRL[gclkn].bit.DIVSEL = 0; - while (pgclk->SYNCBUSY.vec.GENCTRL) { DBGC(DC_CLK_SET_GCLK_FREQ_SYNC_4); } + while (pgclk->SYNCBUSY.vec.GENCTRL) { + DBGC(DC_CLK_SET_GCLK_FREQ_SYNC_4); + } pgclk->GENCTRL[gclkn].bit.GENEN = 1; - while (pgclk->SYNCBUSY.vec.GENCTRL) { DBGC(DC_CLK_SET_GCLK_FREQ_SYNC_5); } + while (pgclk->SYNCBUSY.vec.GENCTRL) { + DBGC(DC_CLK_SET_GCLK_FREQ_SYNC_5); + } system_clks.freq_gclk[gclkn] = system_clks.freq_dpll[0] / pgclk->GENCTRL[gclkn].bit.DIV; DBGC(DC_CLK_SET_GCLK_FREQ_COMPLETE); @@ -103,29 +125,37 @@ uint32_t CLK_set_gclk_freq(uint8_t gclkn, uint32_t freq) return system_clks.freq_gclk[gclkn]; } -void CLK_init_osc(void) -{ +void CLK_init_osc(void) { uint8_t gclkn = GEN_OSC0; - Gclk *pgclk = GCLK; + Gclk * pgclk = GCLK; DBGC(DC_CLK_INIT_OSC_BEGIN); - while (pgclk->SYNCBUSY.vec.GENCTRL) { DBGC(DC_CLK_INIT_OSC_SYNC_1); } + while (pgclk->SYNCBUSY.vec.GENCTRL) { + DBGC(DC_CLK_INIT_OSC_SYNC_1); + } pgclk->GENCTRL[gclkn].bit.SRC = GCLK_SOURCE_XOSC0; - while (pgclk->SYNCBUSY.vec.GENCTRL) { DBGC(DC_CLK_INIT_OSC_SYNC_2); } + while (pgclk->SYNCBUSY.vec.GENCTRL) { + DBGC(DC_CLK_INIT_OSC_SYNC_2); + } pgclk->GENCTRL[gclkn].bit.DIV = 1; - while (pgclk->SYNCBUSY.vec.GENCTRL) { DBGC(DC_CLK_INIT_OSC_SYNC_3); } + while (pgclk->SYNCBUSY.vec.GENCTRL) { + DBGC(DC_CLK_INIT_OSC_SYNC_3); + } pgclk->GENCTRL[gclkn].bit.DIVSEL = 0; - while (pgclk->SYNCBUSY.vec.GENCTRL) { DBGC(DC_CLK_INIT_OSC_SYNC_4); } + while (pgclk->SYNCBUSY.vec.GENCTRL) { + DBGC(DC_CLK_INIT_OSC_SYNC_4); + } pgclk->GENCTRL[gclkn].bit.GENEN = 1; - while (pgclk->SYNCBUSY.vec.GENCTRL) { DBGC(DC_CLK_INIT_OSC_SYNC_5); } + while (pgclk->SYNCBUSY.vec.GENCTRL) { + DBGC(DC_CLK_INIT_OSC_SYNC_5); + } system_clks.freq_gclk[gclkn] = system_clks.freq_xosc0; DBGC(DC_CLK_INIT_OSC_COMPLETE); } -void CLK_reset_time(void) -{ +void CLK_reset_time(void) { Tc *ptc4 = TC4; Tc *ptc0 = TC0; @@ -133,72 +163,85 @@ void CLK_reset_time(void) DBGC(DC_CLK_RESET_TIME_BEGIN); - //stop counters + // stop counters ptc4->COUNT16.CTRLA.bit.ENABLE = 0; - while (ptc4->COUNT16.SYNCBUSY.bit.ENABLE) {} + while (ptc4->COUNT16.SYNCBUSY.bit.ENABLE) { + } ptc0->COUNT32.CTRLA.bit.ENABLE = 0; - while (ptc0->COUNT32.SYNCBUSY.bit.ENABLE) {} - //zero counters + while (ptc0->COUNT32.SYNCBUSY.bit.ENABLE) { + } + // zero counters ptc4->COUNT16.COUNT.reg = 0; - while (ptc4->COUNT16.SYNCBUSY.bit.COUNT) {} + while (ptc4->COUNT16.SYNCBUSY.bit.COUNT) { + } ptc0->COUNT32.COUNT.reg = 0; - while (ptc0->COUNT32.SYNCBUSY.bit.COUNT) {} - //start counters + while (ptc0->COUNT32.SYNCBUSY.bit.COUNT) { + } + // start counters ptc0->COUNT32.CTRLA.bit.ENABLE = 1; - while (ptc0->COUNT32.SYNCBUSY.bit.ENABLE) {} + while (ptc0->COUNT32.SYNCBUSY.bit.ENABLE) { + } ptc4->COUNT16.CTRLA.bit.ENABLE = 1; - while (ptc4->COUNT16.SYNCBUSY.bit.ENABLE) {} + while (ptc4->COUNT16.SYNCBUSY.bit.ENABLE) { + } DBGC(DC_CLK_RESET_TIME_COMPLETE); } -void TC4_Handler() -{ - if (TC4->COUNT16.INTFLAG.bit.MC0) - { +void TC4_Handler() { + if (TC4->COUNT16.INTFLAG.bit.MC0) { TC4->COUNT16.INTFLAG.reg = TC_INTENCLR_MC0; ms_clk++; } } -uint32_t CLK_enable_timebase(void) -{ - Gclk *pgclk = GCLK; - Mclk *pmclk = MCLK; - Tc *ptc4 = TC4; - Tc *ptc0 = TC0; +uint32_t CLK_enable_timebase(void) { + Gclk * pgclk = GCLK; + Mclk * pmclk = MCLK; + Tc * ptc4 = TC4; + Tc * ptc0 = TC0; Evsys *pevsys = EVSYS; DBGC(DC_CLK_ENABLE_TIMEBASE_BEGIN); - //gclk2 highspeed time base + // gclk2 highspeed time base CLK_set_gclk_freq(GEN_TC45, FREQ_TC45_DEFAULT); CLK_init_osc(); - //unmask TC4, sourcegclk2 to TC4 - pmclk->APBCMASK.bit.TC4_ = 1; - pgclk->PCHCTRL[TC4_GCLK_ID].bit.GEN = GEN_TC45; + // unmask TC4, sourcegclk2 to TC4 + pmclk->APBCMASK.bit.TC4_ = 1; + pgclk->PCHCTRL[TC4_GCLK_ID].bit.GEN = GEN_TC45; pgclk->PCHCTRL[TC4_GCLK_ID].bit.CHEN = 1; - //configure TC4 + // configure TC4 DBGC(DC_CLK_ENABLE_TIMEBASE_TC4_BEGIN); ptc4->COUNT16.CTRLA.bit.ENABLE = 0; - while (ptc4->COUNT16.SYNCBUSY.bit.ENABLE) { DBGC(DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_DISABLE); } + while (ptc4->COUNT16.SYNCBUSY.bit.ENABLE) { + DBGC(DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_DISABLE); + } ptc4->COUNT16.CTRLA.bit.SWRST = 1; - while (ptc4->COUNT16.SYNCBUSY.bit.SWRST) { DBGC(DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_SWRST_1); } - while (ptc4->COUNT16.CTRLA.bit.SWRST) { DBGC(DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_SWRST_2); } + while (ptc4->COUNT16.SYNCBUSY.bit.SWRST) { + DBGC(DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_SWRST_1); + } + while (ptc4->COUNT16.CTRLA.bit.SWRST) { + DBGC(DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_SWRST_2); + } - //CTRLA defaults - //CTRLB as default, counting up + // CTRLA defaults + // CTRLB as default, counting up ptc4->COUNT16.CTRLBCLR.reg = 5; - while (ptc4->COUNT16.SYNCBUSY.bit.CTRLB) { DBGC(DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_CLTRB); } + while (ptc4->COUNT16.SYNCBUSY.bit.CTRLB) { + DBGC(DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_CLTRB); + } ptc4->COUNT16.CC[0].reg = 999; - while (ptc4->COUNT16.SYNCBUSY.bit.CC0) { DBGC(DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_CC0); } - //ptc4->COUNT16.DBGCTRL.bit.DBGRUN = 1; + while (ptc4->COUNT16.SYNCBUSY.bit.CC0) { + DBGC(DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_CC0); + } + // ptc4->COUNT16.DBGCTRL.bit.DBGRUN = 1; - //wave mode - ptc4->COUNT16.WAVE.bit.WAVEGEN = 1; //MFRQ match frequency mode, toggle each CC match - //generate event for next stage + // wave mode + ptc4->COUNT16.WAVE.bit.WAVEGEN = 1; // MFRQ match frequency mode, toggle each CC match + // generate event for next stage ptc4->COUNT16.EVCTRL.bit.MCEO0 = 1; NVIC_EnableIRQ(TC4_IRQn); @@ -206,39 +249,45 @@ uint32_t CLK_enable_timebase(void) DBGC(DC_CLK_ENABLE_TIMEBASE_TC4_COMPLETE); - //unmask TC0,1, sourcegclk2 to TC0,1 - pmclk->APBAMASK.bit.TC0_ = 1; - pgclk->PCHCTRL[TC0_GCLK_ID].bit.GEN = GEN_TC45; + // unmask TC0,1, sourcegclk2 to TC0,1 + pmclk->APBAMASK.bit.TC0_ = 1; + pgclk->PCHCTRL[TC0_GCLK_ID].bit.GEN = GEN_TC45; pgclk->PCHCTRL[TC0_GCLK_ID].bit.CHEN = 1; - pmclk->APBAMASK.bit.TC1_ = 1; - pgclk->PCHCTRL[TC1_GCLK_ID].bit.GEN = GEN_TC45; + pmclk->APBAMASK.bit.TC1_ = 1; + pgclk->PCHCTRL[TC1_GCLK_ID].bit.GEN = GEN_TC45; pgclk->PCHCTRL[TC1_GCLK_ID].bit.CHEN = 1; - //configure TC0 + // configure TC0 DBGC(DC_CLK_ENABLE_TIMEBASE_TC0_BEGIN); ptc0->COUNT32.CTRLA.bit.ENABLE = 0; - while (ptc0->COUNT32.SYNCBUSY.bit.ENABLE) { DBGC(DC_CLK_ENABLE_TIMEBASE_TC0_SYNC_DISABLE); } + while (ptc0->COUNT32.SYNCBUSY.bit.ENABLE) { + DBGC(DC_CLK_ENABLE_TIMEBASE_TC0_SYNC_DISABLE); + } ptc0->COUNT32.CTRLA.bit.SWRST = 1; - while (ptc0->COUNT32.SYNCBUSY.bit.SWRST) { DBGC(DC_CLK_ENABLE_TIMEBASE_TC0_SYNC_SWRST_1); } - while (ptc0->COUNT32.CTRLA.bit.SWRST) { DBGC(DC_CLK_ENABLE_TIMEBASE_TC0_SYNC_SWRST_2); } - //CTRLA as default - ptc0->COUNT32.CTRLA.bit.MODE = 2; //32 bit mode - ptc0->COUNT32.EVCTRL.bit.TCEI = 1; //enable incoming events - ptc0->COUNT32.EVCTRL.bit.EVACT = 2 ; //count events + while (ptc0->COUNT32.SYNCBUSY.bit.SWRST) { + DBGC(DC_CLK_ENABLE_TIMEBASE_TC0_SYNC_SWRST_1); + } + while (ptc0->COUNT32.CTRLA.bit.SWRST) { + DBGC(DC_CLK_ENABLE_TIMEBASE_TC0_SYNC_SWRST_2); + } + // CTRLA as default + ptc0->COUNT32.CTRLA.bit.MODE = 2; // 32 bit mode + ptc0->COUNT32.EVCTRL.bit.TCEI = 1; // enable incoming events + ptc0->COUNT32.EVCTRL.bit.EVACT = 2; // count events DBGC(DC_CLK_ENABLE_TIMEBASE_TC0_COMPLETE); DBGC(DC_CLK_ENABLE_TIMEBASE_EVSYS_BEGIN); - //configure event system - pmclk->APBBMASK.bit.EVSYS_ = 1; - pgclk->PCHCTRL[EVSYS_GCLK_ID_0].bit.GEN = GEN_TC45; + // configure event system + pmclk->APBBMASK.bit.EVSYS_ = 1; + pgclk->PCHCTRL[EVSYS_GCLK_ID_0].bit.GEN = GEN_TC45; pgclk->PCHCTRL[EVSYS_GCLK_ID_0].bit.CHEN = 1; - pevsys->USER[44].reg = EVSYS_ID_USER_PORT_EV_0; //TC0 will get event channel 0 - pevsys->Channel[0].CHANNEL.bit.EDGSEL = EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val; //Rising edge - pevsys->Channel[0].CHANNEL.bit.PATH = EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val; //Synchronous - pevsys->Channel[0].CHANNEL.bit.EVGEN = EVSYS_ID_GEN_TC4_MCX_0; //TC4 MC0 + pevsys->USER[44].reg = EVSYS_ID_USER_PORT_EV_0; // TC0 will get event channel 0 + pevsys->Channel[0].CHANNEL.bit.EDGSEL = EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val; // Rising edge + pevsys->Channel[0].CHANNEL.bit.PATH = EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val; // Synchronous + pevsys->Channel[0].CHANNEL.bit.EVGEN = EVSYS_ID_GEN_TC4_MCX_0; // TC4 MC0 DBGC(DC_CLK_ENABLE_TIMEBASE_EVSYS_COMPLETE); @@ -251,34 +300,29 @@ uint32_t CLK_enable_timebase(void) return 0; } -void CLK_delay_us(uint32_t usec) -{ - asm ( - "CBZ R0, return\n\t" //If usec == 0, branch to return label +void CLK_delay_us(uint32_t usec) { + asm("CBZ R0, return\n\t" // If usec == 0, branch to return label ); - asm ( - "MULS R0, %0\n\t" //Multiply R0(usec) by usec_delay_mult and store in R0 - ".balign 16\n\t" //Ensure loop is aligned for fastest performance - "loop: SUBS R0, #1\n\t" //Subtract 1 from R0 and update flags (1 cycle) - "BNE loop\n\t" //Branch if non-zero to loop label (2 cycles) NOTE: USEC_DELAY_LOOP_CYCLES is the sum of loop cycles - "return:\n\t" //Return label - : //No output registers - : "r" (usec_delay_mult) //For %0 + asm("MULS R0, %0\n\t" // Multiply R0(usec) by usec_delay_mult and store in R0 + ".balign 16\n\t" // Ensure loop is aligned for fastest performance + "loop: SUBS R0, #1\n\t" // Subtract 1 from R0 and update flags (1 cycle) + "BNE loop\n\t" // Branch if non-zero to loop label (2 cycles) NOTE: USEC_DELAY_LOOP_CYCLES is the sum of loop cycles + "return:\n\t" // Return label + : // No output registers + : "r"(usec_delay_mult) // For %0 ); - //Note: BX LR generated + // Note: BX LR generated } -void CLK_delay_ms(uint64_t msec) -{ +void CLK_delay_ms(uint64_t msec) { msec += timer_read64(); - while (msec > timer_read64()) {} + while (msec > timer_read64()) { + } } -void clk_enable_sercom_apbmask(int sercomn) -{ +void clk_enable_sercom_apbmask(int sercomn) { Mclk *pmclk = MCLK; - switch (sercomn) - { + switch (sercomn) { case 0: pmclk->APBAMASK.bit.SERCOM0_ = 1; break; @@ -296,26 +340,27 @@ void clk_enable_sercom_apbmask(int sercomn) } } -//call CLK_oscctrl_init first -//call CLK_set_spi_freq(CHAN_SERCOM_SPI, FREQ_SPI_DEFAULT); -uint32_t CLK_set_spi_freq(uint8_t sercomn, uint32_t freq) -{ +// call CLK_oscctrl_init first +// call CLK_set_spi_freq(CHAN_SERCOM_SPI, FREQ_SPI_DEFAULT); +uint32_t CLK_set_spi_freq(uint8_t sercomn, uint32_t freq) { DBGC(DC_CLK_SET_SPI_FREQ_BEGIN); - Gclk *pgclk = GCLK; + Gclk * pgclk = GCLK; Sercom *psercom = (Sercom *)sercom_apbbase[sercomn]; clk_enable_sercom_apbmask(sercomn); - //all gclk0 for now - pgclk->PCHCTRL[sercom_pchan[sercomn]].bit.GEN = 0; + // all gclk0 for now + pgclk->PCHCTRL[sercom_pchan[sercomn]].bit.GEN = 0; pgclk->PCHCTRL[sercom_pchan[sercomn]].bit.CHEN = 1; psercom->I2CM.CTRLA.bit.SWRST = 1; - while (psercom->I2CM.SYNCBUSY.bit.SWRST) {} - while (psercom->I2CM.CTRLA.bit.SWRST) {} + while (psercom->I2CM.SYNCBUSY.bit.SWRST) { + } + while (psercom->I2CM.CTRLA.bit.SWRST) { + } - psercom->SPI.BAUD.reg = (uint8_t) (system_clks.freq_gclk[0]/2/freq-1); - system_clks.freq_spi = system_clks.freq_gclk[0]/2/(psercom->SPI.BAUD.reg+1); + psercom->SPI.BAUD.reg = (uint8_t)(system_clks.freq_gclk[0] / 2 / freq - 1); + system_clks.freq_spi = system_clks.freq_gclk[0] / 2 / (psercom->SPI.BAUD.reg + 1); system_clks.freq_sercom[sercomn] = system_clks.freq_spi; DBGC(DC_CLK_SET_SPI_FREQ_COMPLETE); @@ -323,26 +368,27 @@ uint32_t CLK_set_spi_freq(uint8_t sercomn, uint32_t freq) return system_clks.freq_spi; } -//call CLK_oscctrl_init first -//call CLK_set_i2c0_freq(CHAN_SERCOM_I2C0, FREQ_I2C0_DEFAULT); -uint32_t CLK_set_i2c0_freq(uint8_t sercomn, uint32_t freq) -{ +// call CLK_oscctrl_init first +// call CLK_set_i2c0_freq(CHAN_SERCOM_I2C0, FREQ_I2C0_DEFAULT); +uint32_t CLK_set_i2c0_freq(uint8_t sercomn, uint32_t freq) { DBGC(DC_CLK_SET_I2C0_FREQ_BEGIN); - Gclk *pgclk = GCLK; + Gclk * pgclk = GCLK; Sercom *psercom = (Sercom *)sercom_apbbase[sercomn]; clk_enable_sercom_apbmask(sercomn); - //all gclk0 for now - pgclk->PCHCTRL[sercom_pchan[sercomn]].bit.GEN = 0; + // all gclk0 for now + pgclk->PCHCTRL[sercom_pchan[sercomn]].bit.GEN = 0; pgclk->PCHCTRL[sercom_pchan[sercomn]].bit.CHEN = 1; psercom->I2CM.CTRLA.bit.SWRST = 1; - while (psercom->I2CM.SYNCBUSY.bit.SWRST) {} - while (psercom->I2CM.CTRLA.bit.SWRST) {} + while (psercom->I2CM.SYNCBUSY.bit.SWRST) { + } + while (psercom->I2CM.CTRLA.bit.SWRST) { + } - psercom->I2CM.BAUD.bit.BAUD = (uint8_t) (system_clks.freq_gclk[0]/2/freq-1); - system_clks.freq_i2c0 = system_clks.freq_gclk[0]/2/(psercom->I2CM.BAUD.bit.BAUD+1); + psercom->I2CM.BAUD.bit.BAUD = (uint8_t)(system_clks.freq_gclk[0] / 2 / freq - 1); + system_clks.freq_i2c0 = system_clks.freq_gclk[0] / 2 / (psercom->I2CM.BAUD.bit.BAUD + 1); system_clks.freq_sercom[sercomn] = system_clks.freq_i2c0; DBGC(DC_CLK_SET_I2C0_FREQ_COMPLETE); @@ -350,26 +396,27 @@ uint32_t CLK_set_i2c0_freq(uint8_t sercomn, uint32_t freq) return system_clks.freq_i2c0; } -//call CLK_oscctrl_init first -//call CLK_set_i2c1_freq(CHAN_SERCOM_I2C1, FREQ_I2C1_DEFAULT); -uint32_t CLK_set_i2c1_freq(uint8_t sercomn, uint32_t freq) -{ +// call CLK_oscctrl_init first +// call CLK_set_i2c1_freq(CHAN_SERCOM_I2C1, FREQ_I2C1_DEFAULT); +uint32_t CLK_set_i2c1_freq(uint8_t sercomn, uint32_t freq) { DBGC(DC_CLK_SET_I2C1_FREQ_BEGIN); - Gclk *pgclk = GCLK; + Gclk * pgclk = GCLK; Sercom *psercom = (Sercom *)sercom_apbbase[sercomn]; clk_enable_sercom_apbmask(sercomn); - //all gclk0 for now - pgclk->PCHCTRL[sercom_pchan[sercomn]].bit.GEN = 0; + // all gclk0 for now + pgclk->PCHCTRL[sercom_pchan[sercomn]].bit.GEN = 0; pgclk->PCHCTRL[sercom_pchan[sercomn]].bit.CHEN = 1; psercom->I2CM.CTRLA.bit.SWRST = 1; - while (psercom->I2CM.SYNCBUSY.bit.SWRST) {} - while (psercom->I2CM.CTRLA.bit.SWRST) {} + while (psercom->I2CM.SYNCBUSY.bit.SWRST) { + } + while (psercom->I2CM.CTRLA.bit.SWRST) { + } - psercom->I2CM.BAUD.bit.BAUD = (uint8_t) (system_clks.freq_gclk[0]/2/freq-10); - system_clks.freq_i2c1 = system_clks.freq_gclk[0]/2/(psercom->I2CM.BAUD.bit.BAUD+10); + psercom->I2CM.BAUD.bit.BAUD = (uint8_t)(system_clks.freq_gclk[0] / 2 / freq - 10); + system_clks.freq_i2c1 = system_clks.freq_gclk[0] / 2 / (psercom->I2CM.BAUD.bit.BAUD + 10); system_clks.freq_sercom[sercomn] = system_clks.freq_i2c1; DBGC(DC_CLK_SET_I2C1_FREQ_COMPLETE); @@ -377,15 +424,13 @@ uint32_t CLK_set_i2c1_freq(uint8_t sercomn, uint32_t freq) return system_clks.freq_i2c1; } -void CLK_init(void) -{ +void CLK_init(void) { DBGC(DC_CLK_INIT_BEGIN); - memset((void *)&system_clks,0,sizeof(system_clks)); + memset((void *)&system_clks, 0, sizeof(system_clks)); CLK_oscctrl_init(); CLK_enable_timebase(); DBGC(DC_CLK_INIT_COMPLETE); } - diff --git a/tmk_core/protocol/arm_atsam/clks.h b/tmk_core/protocol/arm_atsam/clks.h index 1b01a1764e..72df3a8e3f 100644 --- a/tmk_core/protocol/arm_atsam/clks.h +++ b/tmk_core/protocol/arm_atsam/clks.h @@ -20,20 +20,20 @@ along with this program. If not, see . #ifndef MD_BOOTLOADER -//From keyboard -#include "config_led.h" -#include "config.h" +// From keyboard +# include "config_led.h" +# include "config.h" -#endif //MD_BOOTLOADER +#endif // MD_BOOTLOADER -#define PLL_RATIO 47 //mcu frequency ((X+1)MHz) -#define FREQ_DFLL_DEFAULT 48000000 //DFLL frequency / usb clock -#define FREQ_SPI_DEFAULT 1000000 //spi to 595 shift regs -#define FREQ_I2C0_DEFAULT 100000 //i2c to hub -#define FREQ_I2C1_DEFAULT I2C_HZ //i2c to LED drivers -#define FREQ_TC45_DEFAULT 1000000 //1 usec resolution +#define PLL_RATIO 47 // mcu frequency ((X+1)MHz) +#define FREQ_DFLL_DEFAULT 48000000 // DFLL frequency / usb clock +#define FREQ_SPI_DEFAULT 1000000 // spi to 595 shift regs +#define FREQ_I2C0_DEFAULT 100000 // i2c to hub +#define FREQ_I2C1_DEFAULT I2C_HZ // i2c to LED drivers +#define FREQ_TC45_DEFAULT 1000000 // 1 usec resolution -//I2C1 Set ~Result PWM Time (2x Drivers) +// I2C1 Set ~Result PWM Time (2x Drivers) // 1000000 1090000 // 900000 1000000 3.82ms // 800000 860000 @@ -42,20 +42,20 @@ along with this program. If not, see . // 580000 615000 6.08ms // 500000 522000 -#define FREQ_XOSC0 16000000 +#define FREQ_XOSC0 16000000 -#define CHAN_SERCOM_SPI 2 //shift regs -#define CHAN_SERCOM_I2C0 0 //hub -#define CHAN_SERCOM_I2C1 1 //led drivers -#define CHAN_SERCOM_UART 3 //debug util +#define CHAN_SERCOM_SPI 2 // shift regs +#define CHAN_SERCOM_I2C0 0 // hub +#define CHAN_SERCOM_I2C1 1 // led drivers +#define CHAN_SERCOM_UART 3 // debug util -//Generator clock channels -#define GEN_DPLL0 0 -#define GEN_OSC0 1 -#define GEN_TC45 2 +// Generator clock channels +#define GEN_DPLL0 0 +#define GEN_OSC0 1 +#define GEN_TC45 2 #define SERCOM_COUNT 5 -#define GCLK_COUNT 12 +#define GCLK_COUNT 12 typedef struct clk_s { uint32_t freq_dfll; @@ -70,20 +70,20 @@ typedef struct clk_s { uint32_t freq_adc0; } clk_t; -extern volatile clk_t system_clks; +extern volatile clk_t system_clks; extern volatile uint64_t ms_clk; -void CLK_oscctrl_init(void); -void CLK_reset_time(void); +void CLK_oscctrl_init(void); +void CLK_reset_time(void); uint32_t CLK_set_gclk_freq(uint8_t gclkn, uint32_t freq); uint32_t CLK_enable_timebase(void); uint64_t timer_read64(void); -void CLK_delay_us(uint32_t usec); -void CLK_delay_ms(uint64_t msec); +void CLK_delay_us(uint32_t usec); +void CLK_delay_ms(uint64_t msec); uint32_t CLK_set_spi_freq(uint8_t sercomn, uint32_t freq); uint32_t CLK_set_i2c0_freq(uint8_t sercomn, uint32_t freq); uint32_t CLK_set_i2c1_freq(uint8_t sercomn, uint32_t freq); -void CLK_init(void); +void CLK_init(void); -#endif // _CLKS_H_ +#endif // _CLKS_H_ diff --git a/tmk_core/protocol/arm_atsam/d51_util.c b/tmk_core/protocol/arm_atsam/d51_util.c index ea42258575..df596f7ba2 100644 --- a/tmk_core/protocol/arm_atsam/d51_util.c +++ b/tmk_core/protocol/arm_atsam/d51_util.c @@ -1,46 +1,50 @@ #include "d51_util.h" static volatile uint32_t w; - -//Display unsigned 32-bit number by port toggling DBG_1 (to view on a scope) -//Read as follows: 1230 = | | | | | | || (note zero is fast double toggle) + +// Display unsigned 32-bit number by port toggling DBG_1 (to view on a scope) +// Read as follows: 1230 = | | | | | | || (note zero is fast double toggle) #define DBG_PAUSE 5 -void dbg_print(uint32_t x) -{ - int8_t t; +void dbg_print(uint32_t x) { + int8_t t; uint32_t n; uint32_t p, p2; - if (x < 10) t = 0; - else if (x < 100) t = 1; - else if (x < 1000) t = 2; - else if (x < 10000) t = 3; - else if (x < 100000) t = 4; - else if (x < 1000000) t = 5; - else if (x < 10000000) t = 6; - else if (x < 100000000) t = 7; - else if (x < 1000000000) t = 8; - else t = 9; - - while (t >= 0) - { + if (x < 10) + t = 0; + else if (x < 100) + t = 1; + else if (x < 1000) + t = 2; + else if (x < 10000) + t = 3; + else if (x < 100000) + t = 4; + else if (x < 1000000) + t = 5; + else if (x < 10000000) + t = 6; + else if (x < 100000000) + t = 7; + else if (x < 1000000000) + t = 8; + else + t = 9; + + while (t >= 0) { p2 = t; - p = 1; + p = 1; while (p2--) p *= 10; n = x / p; x -= n * p; - if (!n) - { + if (!n) { DBG_1_ON; DBG_1_OFF; DBG_1_ON; DBG_1_OFF; n--; - } - else - { - while (n > 0) - { + } else { + while (n > 0) { DBG_1_ON; DBG_1_OFF; n--; @@ -50,68 +54,80 @@ void dbg_print(uint32_t x) t--; } - for (w = DBG_PAUSE; w; w--); //Long pause after number is complete + for (w = DBG_PAUSE; w; w--) + ; // Long pause after number is complete } -//Display unsigned 32-bit number through debug led -//Read as follows: 1230 = [*] [* *] [* * *] [**] (note zero is fast double flash) +// Display unsigned 32-bit number through debug led +// Read as follows: 1230 = [*] [* *] [* * *] [**] (note zero is fast double flash) #define DLED_ONTIME 1000000 #define DLED_PAUSE 1500000 -void dled_print(uint32_t x, uint8_t long_pause) -{ - int8_t t; +void dled_print(uint32_t x, uint8_t long_pause) { + int8_t t; uint32_t n; uint32_t p, p2; - if (x < 10) t = 0; - else if (x < 100) t = 1; - else if (x < 1000) t = 2; - else if (x < 10000) t = 3; - else if (x < 100000) t = 4; - else if (x < 1000000) t = 5; - else if (x < 10000000) t = 6; - else if (x < 100000000) t = 7; - else if (x < 1000000000) t = 8; - else t = 9; - - while (t >= 0) - { + if (x < 10) + t = 0; + else if (x < 100) + t = 1; + else if (x < 1000) + t = 2; + else if (x < 10000) + t = 3; + else if (x < 100000) + t = 4; + else if (x < 1000000) + t = 5; + else if (x < 10000000) + t = 6; + else if (x < 100000000) + t = 7; + else if (x < 1000000000) + t = 8; + else + t = 9; + + while (t >= 0) { p2 = t; - p = 1; + p = 1; while (p2--) p *= 10; n = x / p; x -= n * p; - if (!n) - { + if (!n) { DBG_LED_ON; - for (w = DLED_ONTIME / 4; w; w--); + for (w = DLED_ONTIME / 4; w; w--) + ; DBG_LED_OFF; - for (w = DLED_ONTIME / 4; w; w--); + for (w = DLED_ONTIME / 4; w; w--) + ; DBG_LED_ON; - for (w = DLED_ONTIME / 4; w; w--); + for (w = DLED_ONTIME / 4; w; w--) + ; DBG_LED_OFF; - for (w = DLED_ONTIME / 4; w; w--); + for (w = DLED_ONTIME / 4; w; w--) + ; n--; - } - else - { - while (n > 0) - { + } else { + while (n > 0) { DBG_LED_ON; - for (w = DLED_ONTIME; w; w--); + for (w = DLED_ONTIME; w; w--) + ; DBG_LED_OFF; - for (w = DLED_ONTIME / 2; w; w--); + for (w = DLED_ONTIME / 2; w; w--) + ; n--; } } - for (w = DLED_PAUSE; w; w--); + for (w = DLED_PAUSE; w; w--) + ; t--; } - if (long_pause) - { - for (w = DLED_PAUSE * 4; w; w--); + if (long_pause) { + for (w = DLED_PAUSE * 4; w; w--) + ; } } @@ -119,103 +135,102 @@ void dled_print(uint32_t x, uint8_t long_pause) volatile uint32_t debug_code; -//These macros are for compile time substitution -#define DEBUG_BOOT_TRACING_EXTINTn (DEBUG_BOOT_TRACING_PIN % _U_(0x10)) -#define DEBUG_BOOT_TRACING_EXTINTb (_U_(0x1) << DEBUG_BOOT_TRACING_EXTINTn) -#define DEBUG_BOOT_TRACING_CONFIG_INDn (DEBUG_BOOT_TRACING_EXTINTn / _U_(0x8)) -#define DEBUG_BOOT_TRACING_CONFIG_SENSEn (DEBUG_BOOT_TRACING_EXTINTn % _U_(0x8)) -#define DEBUG_BOOT_TRACING_CONFIG_SENSEb (DEBUG_BOOT_TRACING_CONFIG_SENSEn * _U_(0x4)) -#define DEBUG_BOOT_TRACING_IRQn (EIC_0_IRQn + DEBUG_BOOT_TRACING_EXTINTn) - -//These macros perform PORT+PIN definition translation to IRQn in the preprocessor -#define PORTPIN_TO_IRQn_EXPAND(def) def -#define PORTPIN_TO_IRQn_DEF(def) PORTPIN_TO_IRQn_EXPAND(def) -#if DEBUG_BOOT_TRACING_PIN < 10 -#define PORTPIN_TO_IRQn_TODEF(port, pin) PORTPIN_TO_IRQn_DEF(PIN_ ## port ## 0 ## pin ## A_EIC_EXTINT_NUM) -#else -#define PORTPIN_TO_IRQn_TODEF(port, pin) PORTPIN_TO_IRQn_DEF(PIN_ ## port ## pin ## A_EIC_EXTINT_NUM) -#endif -#define PORTPIN_TO_IRQn(port, pin) PORTPIN_TO_IRQn_TODEF(port, pin) - -//These macros perform function name output in the preprocessor -#define DEBUG_BOOT_TRACING_HANDLER_CONCAT(irq) void EIC_ ## irq ## _Handler(void) -#define DEBUG_BOOT_TRACING_HANDLER(irq) DEBUG_BOOT_TRACING_HANDLER_CONCAT(irq) - -//To generate the function name of the IRQ handler catching boot tracing, +// These macros are for compile time substitution +# define DEBUG_BOOT_TRACING_EXTINTn (DEBUG_BOOT_TRACING_PIN % _U_(0x10)) +# define DEBUG_BOOT_TRACING_EXTINTb (_U_(0x1) << DEBUG_BOOT_TRACING_EXTINTn) +# define DEBUG_BOOT_TRACING_CONFIG_INDn (DEBUG_BOOT_TRACING_EXTINTn / _U_(0x8)) +# define DEBUG_BOOT_TRACING_CONFIG_SENSEn (DEBUG_BOOT_TRACING_EXTINTn % _U_(0x8)) +# define DEBUG_BOOT_TRACING_CONFIG_SENSEb (DEBUG_BOOT_TRACING_CONFIG_SENSEn * _U_(0x4)) +# define DEBUG_BOOT_TRACING_IRQn (EIC_0_IRQn + DEBUG_BOOT_TRACING_EXTINTn) + +// These macros perform PORT+PIN definition translation to IRQn in the preprocessor +# define PORTPIN_TO_IRQn_EXPAND(def) def +# define PORTPIN_TO_IRQn_DEF(def) PORTPIN_TO_IRQn_EXPAND(def) +# if DEBUG_BOOT_TRACING_PIN < 10 +# define PORTPIN_TO_IRQn_TODEF(port, pin) PORTPIN_TO_IRQn_DEF(PIN_##port##0##pin##A_EIC_EXTINT_NUM) +# else +# define PORTPIN_TO_IRQn_TODEF(port, pin) PORTPIN_TO_IRQn_DEF(PIN_##port##pin##A_EIC_EXTINT_NUM) +# endif +# define PORTPIN_TO_IRQn(port, pin) PORTPIN_TO_IRQn_TODEF(port, pin) + +// These macros perform function name output in the preprocessor +# define DEBUG_BOOT_TRACING_HANDLER_CONCAT(irq) void EIC_##irq##_Handler(void) +# define DEBUG_BOOT_TRACING_HANDLER(irq) DEBUG_BOOT_TRACING_HANDLER_CONCAT(irq) + +// To generate the function name of the IRQ handler catching boot tracing, // certain macros must be undefined, so save their current values to macro stack -#pragma push_macro("PA") -#pragma push_macro("PB") -#pragma push_macro("_L_") - -//Undefine / redefine pushed macros -#undef PA -#undef PB -#undef _L_ -#define _L_(x) x - -//Perform the work and output -//Ex: PORT PB, PIN 31 = void EIC_15_Handler(void) +# pragma push_macro("PA") +# pragma push_macro("PB") +# pragma push_macro("_L_") + +// Undefine / redefine pushed macros +# undef PA +# undef PB +# undef _L_ +# define _L_(x) x + +// Perform the work and output +// Ex: PORT PB, PIN 31 = void EIC_15_Handler(void) DEBUG_BOOT_TRACING_HANDLER(PORTPIN_TO_IRQn(DEBUG_BOOT_TRACING_PORT, DEBUG_BOOT_TRACING_PIN)) - -//Restore macros -#pragma pop_macro("PA") -#pragma pop_macro("PB") -#pragma pop_macro("_L_") +// Restore macros +# pragma pop_macro("PA") +# pragma pop_macro("PB") +# pragma pop_macro("_L_") { - //This is only for non-functional keyboard troubleshooting and should be disabled after boot - //Intention is to lock up the keyboard here with repeating debug led code - while (1) - { + // This is only for non-functional keyboard troubleshooting and should be disabled after boot + // Intention is to lock up the keyboard here with repeating debug led code + while (1) { dled_print(debug_code, 1); } } -void debug_code_init(void) -{ +void debug_code_init(void) { DBGC(DC_UNSET); - //Configure Ports for EIC - PORT->Group[DEBUG_BOOT_TRACING_PORT].DIRCLR.reg = 1 << DEBUG_BOOT_TRACING_PIN; //Input - PORT->Group[DEBUG_BOOT_TRACING_PORT].OUTSET.reg = 1 << DEBUG_BOOT_TRACING_PIN; //High - PORT->Group[DEBUG_BOOT_TRACING_PORT].PINCFG[DEBUG_BOOT_TRACING_PIN].bit.INEN = 1; //Input Enable - PORT->Group[DEBUG_BOOT_TRACING_PORT].PINCFG[DEBUG_BOOT_TRACING_PIN].bit.PULLEN = 1; //Pull Enable - PORT->Group[DEBUG_BOOT_TRACING_PORT].PINCFG[DEBUG_BOOT_TRACING_PIN].bit.PMUXEN = 1; //Mux Enable - PORT->Group[DEBUG_BOOT_TRACING_PORT].PMUX[DEBUG_BOOT_TRACING_PIN / 2].bit.PMUXO = 0; //Mux A + // Configure Ports for EIC + PORT->Group[DEBUG_BOOT_TRACING_PORT].DIRCLR.reg = 1 << DEBUG_BOOT_TRACING_PIN; // Input + PORT->Group[DEBUG_BOOT_TRACING_PORT].OUTSET.reg = 1 << DEBUG_BOOT_TRACING_PIN; // High + PORT->Group[DEBUG_BOOT_TRACING_PORT].PINCFG[DEBUG_BOOT_TRACING_PIN].bit.INEN = 1; // Input Enable + PORT->Group[DEBUG_BOOT_TRACING_PORT].PINCFG[DEBUG_BOOT_TRACING_PIN].bit.PULLEN = 1; // Pull Enable + PORT->Group[DEBUG_BOOT_TRACING_PORT].PINCFG[DEBUG_BOOT_TRACING_PIN].bit.PMUXEN = 1; // Mux Enable + PORT->Group[DEBUG_BOOT_TRACING_PORT].PMUX[DEBUG_BOOT_TRACING_PIN / 2].bit.PMUXO = 0; // Mux A - //Enable CLK_EIC_APB + // Enable CLK_EIC_APB MCLK->APBAMASK.bit.EIC_ = 1; - //Configure EIC + // Configure EIC EIC->CTRLA.bit.SWRST = 1; - while (EIC->SYNCBUSY.bit.SWRST) {} - EIC->ASYNCH.reg = DEBUG_BOOT_TRACING_EXTINTb; + while (EIC->SYNCBUSY.bit.SWRST) { + } + EIC->ASYNCH.reg = DEBUG_BOOT_TRACING_EXTINTb; EIC->INTENSET.reg = DEBUG_BOOT_TRACING_EXTINTb; EIC->CONFIG[DEBUG_BOOT_TRACING_CONFIG_INDn].reg |= (EIC_CONFIG_SENSE0_FALL_Val << DEBUG_BOOT_TRACING_CONFIG_SENSEb); EIC->CTRLA.bit.ENABLE = 1; - while (EIC->SYNCBUSY.bit.ENABLE) {} + while (EIC->SYNCBUSY.bit.ENABLE) { + } - //E