| Commit message (Collapse) | Author | Age | Files | Lines |
|---|
| | |
|
| | |
|
| | |
|
| | |
|
| |
|
|
|
|
|
|
|
|
|
| |
Previously, if the user tried to use `#define AUDIO_MAX_SIMULTANEOUS_TONES 1` to conserve CPU time, their firmware would fail to build with this error:
```
platforms/chibios/drivers/audio_dac_additive.c:91:73: error: excess elements in array initializer [-Werror]
91 | static float active_tones_snapshot[AUDIO_MAX_SIMULTANEOUS_TONES] = {0, 0};
| ^
```
This also affected the preset `#define AUDIO_DAC_QUALITY_VERY_HIGH`, which called up only one simultaneous tone at 88200 Hz.
|
| | |
|
| | |
|
| | |
|
| | |
|
| | |
|
| | |
|
| |
|
|
| |
`KEEP_INTERMEDIATES=yes`. (#20339)
|
| | |
|
| |
|
|
| |
Co-authored-by: Johannes H. Jensen <joh@pseudoberries.com>
|
| |
|
|
|
|
|
|
|
|
| |
The `adc_read()` code for STM32F0xx expects to get the 0-based channel
number in `mux.input`, but the `pinToMux()` code for STM32F0xx was
attempting to pass the CHSELR bit mask in that field, which resulted in
selecting a wrong channel, therefore `analogReadPin()` did not work
properly for the STM32F0xx chips. Fix `pinToMux()` to put the channel
number in that field (this matches the behavior for other supported
chips and also allows selection of channels 16...18, which can be used
to access the builtin temperature, reference voltage and VBAT sensors).
|
| |
|
| |
Co-authored-by: Sergey Vlasov <sigprof@gmail.com>
|
| | |
|
| |
|
|
|
| |
* Fix functions with empty params
* Found a bunch more
|
| |
|
| |
Co-authored-by: Ryan <fauxpark@gmail.com>
|
| |
|
| |
Co-authored-by: Nick Brassel <nick@tzarc.org>
|
| | |
|
| |
|
|
|
|
|
| |
* Rename `eeprom_stm32` to `eeprom_legacy_emulated_flash`.
* Rename `flash_stm32` to `legacy_flash_ops`.
* Rename `eeprom_teensy` to `eeprom_kinetis_flexram`.
|
| |
|
|
| |
GD32V. (#19020)
|
| | |
|
| | |
|
| |
|
| |
Co-authored-by: Joy <chang.li@westberrytech.com>
|
| | |
|
| |
|
|
| |
from RGBLEDs/RGBMATRIX defines (#18036)
|
| | |
|
| |
|
|
| |
keyboard (#18419)
|
| |
|
|
|
|
| |
...by moving the actually timing critical `enter_rx_state()` and
`leave_rx_state()` functions to RAM in order to not be affected by XIP
cache spikes. This commit also reverts the hacky USB interrupt disabling
that was done in 293c53d774
|
| |
|
|
|
| |
* Add UART support for Kinetis boards
* Default PAL mode for GPIOV1
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
* Add ARRAY_SIZE and CEILING utility macros
* Apply a coccinelle patch to use ARRAY_SIZE
* fix up some straggling items
* Fix 'make test:secure'
* Enhance ARRAY_SIZE macro to reject acting on pointers
The previous definition would not produce a diagnostic for
```
int *p;
size_t num_elem = ARRAY_SIZE(p)
```
but the new one will.
* explicitly get definition of ARRAY_SIZE
* Convert to ARRAY_SIZE when const is involved
The following spatch finds additional instances where the array is
const and the division is by the size of the type, not the size of
the first element:
```
@ rule5a using "empty.iso" @
type T;
const T[] E;
@@
- (sizeof(E)/sizeof(T))
+ ARRAY_SIZE(E)
@ rule6a using "empty.iso" @
type T;
const T[] E;
@@
- sizeof(E)/sizeof(T)
+ ARRAY_SIZE(E)
```
* New instances of ARRAY_SIZE added since initial spatch run
* Use `ARRAY_SIZE` in docs (found by grep)
* Manually use ARRAY_SIZE
hs_set is expected to be the same size as uint16_t, though it's made
of two 8-bit integers
* Just like char, sizeof(uint8_t) is guaranteed to be 1
This is at least true on any plausible system where qmk is actually used.
Per my understanding it's universally true, assuming that uint8_t exists:
https://stackoverflow.com/questions/48655310/can-i-assume-that-sizeofuint8-t-1
* Run qmk-format on core C files touched in this branch
Co-authored-by: Stefan Kerkmann <karlk90@pm.me>
|
| | |
|
| | |
|
| |
|
|
|
| |
Co-authored-by: Drashna Jaelre <drashna@live.com>
Co-authored-by: Sergey Vlasov <sigprof@gmail.com>
Co-authored-by: yiancar <yiancar@gmail.com>
|
| |
|
| |
Co-authored-by: Joy <chang.li@westberrytech.com>
|
| |
|
| |
Co-authored-by: Joy <chang.li@westberrytech.com>
|
| | |
|
| | |
|
| | |
|
| | |
|
| |
|
|
| |
msg_t is MSG_OK in the success case and either MSG_RESET or MSG_TIMEOUT
in case of errors. So actually use them in the comparison.
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
| |
From the ChibiOS HAL I2C driver pages:
After a timeout the driver must be stopped and restarted because the bus is in
an uncertain state.
This commit does that stopping explicitly on any error that occurred, not only
timeouts. As all the i2c functions restart the peripheral if necessary it is
safe to do so.
Co-authored-by: Dasky <32983009+daskygit@users.noreply.github.com>
Co-authored-by: Dasky <32983009+daskygit@users.noreply.github.com>
|
| |
|
|
|
|
|
| |
* Fixup read address for EFL driver.
* Fixup sequencing of SPI.
* Lock during init of EFL backing store.
|
| | |
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
* Use polled waiting on platforms that support it
Due to context switching overhead waiting a very short amount of time on
a sleeping thread is often not accurate and in fact not usable for timing
critical usage i.e. in a driver. Thus we use polled waiting for ranges
in the us range on platforms that support it instead. The fallback is
the thread sleeping mechanism.
This includes:
* ARM platforms with CYCCNT register (ARMv7, ARMv8) this is
incremented at CPU clock frequency
* GD32VF103 RISC-V port with CSR_MCYCLE register this is incremented at
CPU clock frequency
* RP2040 ARMv6 port which uses the integrated timer peripheral which is
incremented with a fixed 1MHz frequency
* Use wait_us() instead of chSysPolledDelayX
...as it is powered by busy waiting now.
* Add chibios waiting methods test bench
|
| | |
|
| | |
|
| | |
|
