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-rw-r--r--platforms/chibios/drivers/analog.c321
-rw-r--r--platforms/chibios/drivers/analog.h41
-rw-r--r--platforms/chibios/drivers/eeprom/eeprom_stm32_L0_L1.c96
-rw-r--r--platforms/chibios/drivers/eeprom/eeprom_stm32_L0_L1.h33
-rw-r--r--platforms/chibios/drivers/i2c_master.c121
-rw-r--r--platforms/chibios/drivers/i2c_master.h113
-rw-r--r--platforms/chibios/drivers/serial.c278
-rw-r--r--platforms/chibios/drivers/serial_usart.c318
-rw-r--r--platforms/chibios/drivers/serial_usart.h116
-rw-r--r--platforms/chibios/drivers/spi_master.c202
-rw-r--r--platforms/chibios/drivers/spi_master.h93
-rw-r--r--platforms/chibios/drivers/uart.c50
-rw-r--r--platforms/chibios/drivers/uart.h77
-rw-r--r--platforms/chibios/drivers/usbpd_stm32g4.c76
-rw-r--r--platforms/chibios/drivers/ws2812.c114
-rw-r--r--platforms/chibios/drivers/ws2812_pwm.c311
-rw-r--r--platforms/chibios/drivers/ws2812_spi.c159
17 files changed, 2519 insertions, 0 deletions
diff --git a/platforms/chibios/drivers/analog.c b/platforms/chibios/drivers/analog.c
new file mode 100644
index 0000000000..8c476fcac2
--- /dev/null
+++ b/platforms/chibios/drivers/analog.c
@@ -0,0 +1,321 @@
+/* Copyright 2019 Drew Mills
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "quantum.h"
+#include "analog.h"
+#include <ch.h>
+#include <hal.h>
+
+#if !HAL_USE_ADC
+# error "You need to set HAL_USE_ADC to TRUE in your halconf.h to use the ADC."
+#endif
+
+#if !STM32_ADC_USE_ADC1 && !STM32_ADC_USE_ADC2 && !STM32_ADC_USE_ADC3 && !STM32_ADC_USE_ADC4
+# error "You need to set one of the 'STM32_ADC_USE_ADCx' settings to TRUE in your mcuconf.h to use the ADC."
+#endif
+
+#if STM32_ADC_DUAL_MODE
+# error "STM32 ADC Dual Mode is not supported at this time."
+#endif
+
+#if STM32_ADCV3_OVERSAMPLING
+# error "STM32 ADCV3 Oversampling is not supported at this time."
+#endif
+
+// Otherwise assume V3
+#if defined(STM32F0XX) || defined(STM32L0XX)
+# define USE_ADCV1
+#elif defined(STM32F1XX) || defined(STM32F2XX) || defined(STM32F4XX)
+# define USE_ADCV2
+#endif
+
+// BODGE to make v2 look like v1,3 and 4
+#ifdef USE_ADCV2
+# if !defined(ADC_SMPR_SMP_1P5) && defined(ADC_SAMPLE_3)
+# define ADC_SMPR_SMP_1P5 ADC_SAMPLE_3
+# define ADC_SMPR_SMP_7P5 ADC_SAMPLE_15
+# define ADC_SMPR_SMP_13P5 ADC_SAMPLE_28
+# define ADC_SMPR_SMP_28P5 ADC_SAMPLE_56
+# define ADC_SMPR_SMP_41P5 ADC_SAMPLE_84
+# define ADC_SMPR_SMP_55P5 ADC_SAMPLE_112
+# define ADC_SMPR_SMP_71P5 ADC_SAMPLE_144
+# define ADC_SMPR_SMP_239P5 ADC_SAMPLE_480
+# endif
+
+# if !defined(ADC_SMPR_SMP_1P5) && defined(ADC_SAMPLE_1P5)
+# define ADC_SMPR_SMP_1P5 ADC_SAMPLE_1P5
+# define ADC_SMPR_SMP_7P5 ADC_SAMPLE_7P5
+# define ADC_SMPR_SMP_13P5 ADC_SAMPLE_13P5
+# define ADC_SMPR_SMP_28P5 ADC_SAMPLE_28P5
+# define ADC_SMPR_SMP_41P5 ADC_SAMPLE_41P5
+# define ADC_SMPR_SMP_55P5 ADC_SAMPLE_55P5
+# define ADC_SMPR_SMP_71P5 ADC_SAMPLE_71P5
+# define ADC_SMPR_SMP_239P5 ADC_SAMPLE_239P5
+# endif
+
+// we still sample at 12bit, but scale down to the requested bit range
+# define ADC_CFGR1_RES_12BIT 12
+# define ADC_CFGR1_RES_10BIT 10
+# define ADC_CFGR1_RES_8BIT 8
+# define ADC_CFGR1_RES_6BIT 6
+#endif
+
+/* User configurable ADC options */
+#ifndef ADC_COUNT
+# if defined(STM32F0XX) || defined(STM32F1XX) || defined(STM32F4XX)
+# define ADC_COUNT 1
+# elif defined(STM32F3XX)
+# define ADC_COUNT 4
+# else
+# error "ADC_COUNT has not been set for this ARM microcontroller."
+# endif
+#endif
+
+#ifndef ADC_NUM_CHANNELS
+# define ADC_NUM_CHANNELS 1
+#elif ADC_NUM_CHANNELS != 1
+# error "The ARM ADC implementation currently only supports reading one channel at a time."
+#endif
+
+#ifndef ADC_BUFFER_DEPTH
+# define ADC_BUFFER_DEPTH 1
+#endif
+
+// For more sampling rate options, look at hal_adc_lld.h in ChibiOS
+#ifndef ADC_SAMPLING_RATE
+# define ADC_SAMPLING_RATE ADC_SMPR_SMP_1P5
+#endif
+
+// Options are 12, 10, 8, and 6 bit.
+#ifndef ADC_RESOLUTION
+# ifdef ADC_CFGR_RES_10BITS // ADCv3, ADCv4
+# define ADC_RESOLUTION ADC_CFGR_RES_10BITS
+# else // ADCv1, ADCv5, or the bodge for ADCv2 above
+# define ADC_RESOLUTION ADC_CFGR1_RES_10BIT
+# endif
+#endif
+
+static ADCConfig adcCfg = {};
+static adcsample_t sampleBuffer[ADC_NUM_CHANNELS * ADC_BUFFER_DEPTH];
+
+// Initialize to max number of ADCs, set to empty object to initialize all to false.
+static bool adcInitialized[ADC_COUNT] = {};
+
+// TODO: add back TR handling???
+static ADCConversionGroup adcConversionGroup = {
+ .circular = FALSE,
+ .num_channels = (uint16_t)(ADC_NUM_CHANNELS),
+#if defined(USE_ADCV1)
+ .cfgr1 = ADC_CFGR1_CONT | ADC_RESOLUTION,
+ .smpr = ADC_SAMPLING_RATE,
+#elif defined(USE_ADCV2)
+# if !defined(STM32F1XX)
+ .cr2 = ADC_CR2_SWSTART, // F103 seem very unhappy with, F401 seems very unhappy without...
+# endif
+ .smpr2 = ADC_SMPR2_SMP_AN0(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN1(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN2(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN3(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN4(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN5(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN6(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN7(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN8(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN9(ADC_SAMPLING_RATE),
+ .smpr1 = ADC_SMPR1_SMP_AN10(ADC_SAMPLING_RATE) | ADC_SMPR1_SMP_AN11(ADC_SAMPLING_RATE) | ADC_SMPR1_SMP_AN12(ADC_SAMPLING_RATE) | ADC_SMPR1_SMP_AN13(ADC_SAMPLING_RATE) | ADC_SMPR1_SMP_AN14(ADC_SAMPLING_RATE) | ADC_SMPR1_SMP_AN15(ADC_SAMPLING_RATE),
+#else
+ .cfgr = ADC_CFGR_CONT | ADC_RESOLUTION,
+ .smpr = {ADC_SMPR1_SMP_AN0(ADC_SAMPLING_RATE) | ADC_SMPR1_SMP_AN1(ADC_SAMPLING_RATE) | ADC_SMPR1_SMP_AN2(ADC_SAMPLING_RATE) | ADC_SMPR1_SMP_AN3(ADC_SAMPLING_RATE) | ADC_SMPR1_SMP_AN4(ADC_SAMPLING_RATE) | ADC_SMPR1_SMP_AN5(ADC_SAMPLING_RATE) | ADC_SMPR1_SMP_AN6(ADC_SAMPLING_RATE) | ADC_SMPR1_SMP_AN7(ADC_SAMPLING_RATE) | ADC_SMPR1_SMP_AN8(ADC_SAMPLING_RATE) | ADC_SMPR1_SMP_AN9(ADC_SAMPLING_RATE), ADC_SMPR2_SMP_AN10(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN11(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN12(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN13(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN14(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN15(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN16(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN17(ADC_SAMPLING_RATE) | ADC_SMPR2_SMP_AN18(ADC_SAMPLING_RATE)},
+#endif
+};
+
+// clang-format off
+__attribute__((weak)) adc_mux pinToMux(pin_t pin) {
+ switch (pin) {
+#if defined(STM32F0XX)
+ case A0: return TO_MUX( ADC_CHSELR_CHSEL0, 0 );
+ case A1: return TO_MUX( ADC_CHSELR_CHSEL1, 0 );
+ case A2: return TO_MUX( ADC_CHSELR_CHSEL2, 0 );
+ case A3: return TO_MUX( ADC_CHSELR_CHSEL3, 0 );
+ case A4: return TO_MUX( ADC_CHSELR_CHSEL4, 0 );
+ case A5: return TO_MUX( ADC_CHSELR_CHSEL5, 0 );
+ case A6: return TO_MUX( ADC_CHSELR_CHSEL6, 0 );
+ case A7: return TO_MUX( ADC_CHSELR_CHSEL7, 0 );
+ case B0: return TO_MUX( ADC_CHSELR_CHSEL8, 0 );
+ case B1: return TO_MUX( ADC_CHSELR_CHSEL9, 0 );
+ case C0: return TO_MUX( ADC_CHSELR_CHSEL10, 0 );
+ case C1: return TO_MUX( ADC_CHSELR_CHSEL11, 0 );
+ case C2: return TO_MUX( ADC_CHSELR_CHSEL12, 0 );
+ case C3: return TO_MUX( ADC_CHSELR_CHSEL13, 0 );
+ case C4: return TO_MUX( ADC_CHSELR_CHSEL14, 0 );
+ case C5: return TO_MUX( ADC_CHSELR_CHSEL15, 0 );
+#elif defined(STM32F3XX)
+ case A0: return TO_MUX( ADC_CHANNEL_IN1, 0 );
+ case A1: return TO_MUX( ADC_CHANNEL_IN2, 0 );
+ case A2: return TO_MUX( ADC_CHANNEL_IN3, 0 );
+ case A3: return TO_MUX( ADC_CHANNEL_IN4, 0 );
+ case A4: return TO_MUX( ADC_CHANNEL_IN1, 1 );
+ case A5: return TO_MUX( ADC_CHANNEL_IN2, 1 );
+ case A6: return TO_MUX( ADC_CHANNEL_IN3, 1 );
+ case A7: return TO_MUX( ADC_CHANNEL_IN4, 1 );
+ case B0: return TO_MUX( ADC_CHANNEL_IN12, 2 );
+ case B1: return TO_MUX( ADC_CHANNEL_IN1, 2 );
+ case B2: return TO_MUX( ADC_CHANNEL_IN12, 1 );
+ case B12: return TO_MUX( ADC_CHANNEL_IN3, 3 );
+ case B13: return TO_MUX( ADC_CHANNEL_IN5, 2 );
+ case B14: return TO_MUX( ADC_CHANNEL_IN4, 3 );
+ case B15: return TO_MUX( ADC_CHANNEL_IN5, 3 );
+ case C0: return TO_MUX( ADC_CHANNEL_IN6, 0 ); // Can also be ADC2
+ case C1: return TO_MUX( ADC_CHANNEL_IN7, 0 ); // Can also be ADC2
+ case C2: return TO_MUX( ADC_CHANNEL_IN8, 0 ); // Can also be ADC2
+ case C3: return TO_MUX( ADC_CHANNEL_IN9, 0 ); // Can also be ADC2
+ case C4: return TO_MUX( ADC_CHANNEL_IN5, 1 );
+ case C5: return TO_MUX( ADC_CHANNEL_IN11, 1 );
+ case D8: return TO_MUX( ADC_CHANNEL_IN12, 3 );
+ case D9: return TO_MUX( ADC_CHANNEL_IN13, 3 );
+ case D10: return TO_MUX( ADC_CHANNEL_IN7, 2 ); // Can also be ADC4
+ case D11: return TO_MUX( ADC_CHANNEL_IN8, 2 ); // Can also be ADC4
+ case D12: return TO_MUX( ADC_CHANNEL_IN9, 2 ); // Can also be ADC4
+ case D13: return TO_MUX( ADC_CHANNEL_IN10, 2 ); // Can also be ADC4
+ case D14: return TO_MUX( ADC_CHANNEL_IN11, 2 ); // Can also be ADC4
+ case E7: return TO_MUX( ADC_CHANNEL_IN13, 2 );
+ case E8: return TO_MUX( ADC_CHANNEL_IN6, 2 ); // Can also be ADC4
+ case E9: return TO_MUX( ADC_CHANNEL_IN2, 2 );
+ case E10: return TO_MUX( ADC_CHANNEL_IN14, 2 );
+ case E11: return TO_MUX( ADC_CHANNEL_IN15, 2 );
+ case E12: return TO_MUX( ADC_CHANNEL_IN16, 2 );
+ case E13: return TO_MUX( ADC_CHANNEL_IN3, 2 );
+ case E14: return TO_MUX( ADC_CHANNEL_IN1, 3 );
+ case E15: return TO_MUX( ADC_CHANNEL_IN2, 3 );
+ case F2: return TO_MUX( ADC_CHANNEL_IN10, 0 ); // Can also be ADC2
+ case F4: return TO_MUX( ADC_CHANNEL_IN5, 0 );
+#elif defined(STM32F4XX)
+ case A0: return TO_MUX( ADC_CHANNEL_IN0, 0 );
+ case A1: return TO_MUX( ADC_CHANNEL_IN1, 0 );
+ case A2: return TO_MUX( ADC_CHANNEL_IN2, 0 );
+ case A3: return TO_MUX( ADC_CHANNEL_IN3, 0 );
+ case A4: return TO_MUX( ADC_CHANNEL_IN4, 0 );
+ case A5: return TO_MUX( ADC_CHANNEL_IN5, 0 );
+ case A6: return TO_MUX( ADC_CHANNEL_IN6, 0 );
+ case A7: return TO_MUX( ADC_CHANNEL_IN7, 0 );
+ case B0: return TO_MUX( ADC_CHANNEL_IN8, 0 );
+ case B1: return TO_MUX( ADC_CHANNEL_IN9, 0 );
+ case C0: return TO_MUX( ADC_CHANNEL_IN10, 0 );
+ case C1: return TO_MUX( ADC_CHANNEL_IN11, 0 );
+ case C2: return TO_MUX( ADC_CHANNEL_IN12, 0 );
+ case C3: return TO_MUX( ADC_CHANNEL_IN13, 0 );
+ case C4: return TO_MUX( ADC_CHANNEL_IN14, 0 );
+ case C5: return TO_MUX( ADC_CHANNEL_IN15, 0 );
+# if STM32_ADC_USE_ADC3
+ case F3: return TO_MUX( ADC_CHANNEL_IN9, 2 );
+ case F4: return TO_MUX( ADC_CHANNEL_IN14, 2 );
+ case F5: return TO_MUX( ADC_CHANNEL_IN15, 2 );
+ case F6: return TO_MUX( ADC_CHANNEL_IN4, 2 );
+ case F7: return TO_MUX( ADC_CHANNEL_IN5, 2 );
+ case F8: return TO_MUX( ADC_CHANNEL_IN6, 2 );
+ case F9: return TO_MUX( ADC_CHANNEL_IN7, 2 );
+ case F10: return TO_MUX( ADC_CHANNEL_IN8, 2 );
+# endif
+#elif defined(STM32F1XX)
+ case A0: return TO_MUX( ADC_CHANNEL_IN0, 0 );
+ case A1: return TO_MUX( ADC_CHANNEL_IN1, 0 );
+ case A2: return TO_MUX( ADC_CHANNEL_IN2, 0 );
+ case A3: return TO_MUX( ADC_CHANNEL_IN3, 0 );
+ case A4: return TO_MUX( ADC_CHANNEL_IN4, 0 );
+ case A5: return TO_MUX( ADC_CHANNEL_IN5, 0 );
+ case A6: return TO_MUX( ADC_CHANNEL_IN6, 0 );
+ case A7: return TO_MUX( ADC_CHANNEL_IN7, 0 );
+ case B0: return TO_MUX( ADC_CHANNEL_IN8, 0 );
+ case B1: return TO_MUX( ADC_CHANNEL_IN9, 0 );
+ case C0: return TO_MUX( ADC_CHANNEL_IN10, 0 );
+ case C1: return TO_MUX( ADC_CHANNEL_IN11, 0 );
+ case C2: return TO_MUX( ADC_CHANNEL_IN12, 0 );
+ case C3: return TO_MUX( ADC_CHANNEL_IN13, 0 );
+ case C4: return TO_MUX( ADC_CHANNEL_IN14, 0 );
+ case C5: return TO_MUX( ADC_CHANNEL_IN15, 0 );
+ // STM32F103x[C-G] in 144-pin packages also have analog inputs on F6...F10, but they are on ADC3, and the
+ // ChibiOS ADC driver for STM32F1xx currently supports only ADC1, therefore these pins are not usable.
+#endif
+ }
+
+ // return an adc that would never be used so intToADCDriver will bail out
+ return TO_MUX(0, 0xFF);
+}
+// clang-format on
+
+static inline ADCDriver* intToADCDriver(uint8_t adcInt) {
+ switch (adcInt) {
+#if STM32_ADC_USE_ADC1
+ case 0:
+ return &ADCD1;
+#endif
+#if STM32_ADC_USE_ADC2
+ case 1:
+ return &ADCD2;
+#endif
+#if STM32_ADC_USE_ADC3
+ case 2:
+ return &ADCD3;
+#endif
+#if STM32_ADC_USE_ADC4
+ case 3:
+ return &ADCD4;
+#endif
+ }
+
+ return NULL;
+}
+
+static inline void manageAdcInitializationDriver(uint8_t adc, ADCDriver* adcDriver) {
+ if (!adcInitialized[adc]) {
+ adcStart(adcDriver, &adcCfg);
+ adcInitialized[adc] = true;
+ }
+}
+
+int16_t analogReadPin(pin_t pin) {
+ palSetLineMode(pin, PAL_MODE_INPUT_ANALOG);
+
+ return adc_read(pinToMux(pin));
+}
+
+int16_t analogReadPinAdc(pin_t pin, uint8_t adc) {
+ palSetLineMode(pin, PAL_MODE_INPUT_ANALOG);
+
+ adc_mux target = pinToMux(pin);
+ target.adc = adc;
+ return adc_read(target);
+}
+
+int16_t adc_read(adc_mux mux) {
+#if defined(USE_ADCV1)
+ // TODO: fix previous assumption of only 1 input...
+ adcConversionGroup.chselr = 1 << mux.input; /*no macro to convert N to ADC_CHSELR_CHSEL1*/
+#elif defined(USE_ADCV2)
+ adcConversionGroup.sqr3 = ADC_SQR3_SQ1_N(mux.input);
+#else
+ adcConversionGroup.sqr[0] = ADC_SQR1_SQ1_N(mux.input);
+#endif
+
+ ADCDriver* targetDriver = intToADCDriver(mux.adc);
+ if (!targetDriver) {
+ return 0;
+ }
+
+ manageAdcInitializationDriver(mux.adc, targetDriver);
+ if (adcConvert(targetDriver, &adcConversionGroup, &sampleBuffer[0], ADC_BUFFER_DEPTH) != MSG_OK) {
+ return 0;
+ }
+
+#ifdef USE_ADCV2
+ // fake 12-bit -> N-bit scale
+ return (*sampleBuffer) >> (12 - ADC_RESOLUTION);
+#else
+ // already handled as part of adcConvert
+ return *sampleBuffer;
+#endif
+}
diff --git a/platforms/chibios/drivers/analog.h b/platforms/chibios/drivers/analog.h
new file mode 100644
index 0000000000..e61c394265
--- /dev/null
+++ b/platforms/chibios/drivers/analog.h
@@ -0,0 +1,41 @@
+/* Copyright 2019 Drew Mills
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#include <stdint.h>
+#include "quantum.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+ uint16_t input;
+ uint8_t adc;
+} adc_mux;
+#define TO_MUX(i, a) \
+ (adc_mux) { i, a }
+
+int16_t analogReadPin(pin_t pin);
+int16_t analogReadPinAdc(pin_t pin, uint8_t adc);
+adc_mux pinToMux(pin_t pin);
+
+int16_t adc_read(adc_mux mux);
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/platforms/chibios/drivers/eeprom/eeprom_stm32_L0_L1.c b/platforms/chibios/drivers/eeprom/eeprom_stm32_L0_L1.c
new file mode 100644
index 0000000000..ed26cc7145
--- /dev/null
+++ b/platforms/chibios/drivers/eeprom/eeprom_stm32_L0_L1.c
@@ -0,0 +1,96 @@
+/* Copyright 2020 Nick Brassel (tzarc)
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <stdint.h>
+#include <string.h>
+
+#include <hal.h>
+#include "eeprom_driver.h"
+#include "eeprom_stm32_L0_L1.h"
+
+#define EEPROM_BASE_ADDR 0x08080000
+#define EEPROM_ADDR(offset) (EEPROM_BASE_ADDR + (offset))
+#define EEPROM_PTR(offset) ((__IO uint8_t *)EEPROM_ADDR(offset))
+#define EEPROM_BYTE(location, offset) (*(EEPROM_PTR(((uint32_t)location) + ((uint32_t)offset))))
+
+#define BUFFER_BYTE(buffer, offset) (*(((uint8_t *)buffer) + offset))
+
+#define FLASH_PEKEY1 0x89ABCDEF
+#define FLASH_PEKEY2 0x02030405
+
+static inline void STM32_L0_L1_EEPROM_WaitNotBusy(void) {
+ while (FLASH->SR & FLASH_SR_BSY) {
+ __WFI();
+ }
+}
+
+static inline void STM32_L0_L1_EEPROM_Unlock(void) {
+ STM32_L0_L1_EEPROM_WaitNotBusy();
+ if (FLASH->PECR & FLASH_PECR_PELOCK) {
+ FLASH->PEKEYR = FLASH_PEKEY1;
+ FLASH->PEKEYR = FLASH_PEKEY2;
+ }
+}
+
+static inline void STM32_L0_L1_EEPROM_Lock(void) {
+ STM32_L0_L1_EEPROM_WaitNotBusy();
+ FLASH->PECR |= FLASH_PECR_PELOCK;
+}
+
+void eeprom_driver_init(void) {}
+
+void eeprom_driver_erase(void) {
+ STM32_L0_L1_EEPROM_Unlock();
+
+ for (size_t offset = 0; offset < STM32_ONBOARD_EEPROM_SIZE; offset += sizeof(uint32_t)) {
+ FLASH->PECR |= FLASH_PECR_ERASE | FLASH_PECR_DATA;
+
+ *(__IO uint32_t *)EEPROM_ADDR(offset) = (uint32_t)0;
+
+ STM32_L0_L1_EEPROM_WaitNotBusy();
+ FLASH->PECR &= ~(FLASH_PECR_ERASE | FLASH_PECR_DATA);
+ }
+
+ STM32_L0_L1_EEPROM_Lock();
+}
+
+void eeprom_read_block(void *buf, const void *addr, size_t len) {
+ for (size_t offset = 0; offset < len; ++offset) {
+ // Drop out if we've hit the limit of the EEPROM
+ if ((((uint32_t)addr) + offset) >= STM32_ONBOARD_EEPROM_SIZE) {
+ break;
+ }
+
+ STM32_L0_L1_EEPROM_WaitNotBusy();
+ BUFFER_BYTE(buf, offset) = EEPROM_BYTE(addr, offset);
+ }
+}
+
+void eeprom_write_block(const void *buf, void *addr, size_t len) {
+ STM32_L0_L1_EEPROM_Unlock();
+
+ for (size_t offset = 0; offset < len; ++offset) {
+ // Drop out if we've hit the limit of the EEPROM
+ if ((((uint32_t)addr) + offset) >= STM32_ONBOARD_EEPROM_SIZE) {
+ break;
+ }
+
+ STM32_L0_L1_EEPROM_WaitNotBusy();
+ EEPROM_BYTE(addr, offset) = BUFFER_BYTE(buf, offset);
+ }
+
+ STM32_L0_L1_EEPROM_Lock();
+}
diff --git a/platforms/chibios/drivers/eeprom/eeprom_stm32_L0_L1.h b/platforms/chibios/drivers/eeprom/eeprom_stm32_L0_L1.h
new file mode 100644
index 0000000000..a35defca8b
--- /dev/null
+++ b/platforms/chibios/drivers/eeprom/eeprom_stm32_L0_L1.h
@@ -0,0 +1,33 @@
+/* Copyright 2020 Nick Brassel (tzarc)
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+/*
+ The size used by the STM32 L0/L1 EEPROM driver.
+*/
+#ifndef STM32_ONBOARD_EEPROM_SIZE
+# ifdef VIA_ENABLE
+# define STM32_ONBOARD_EEPROM_SIZE 1024
+# else
+# include "eeconfig.h"
+# define STM32_ONBOARD_EEPROM_SIZE (((EECONFIG_SIZE + 3) / 4) * 4) // based off eeconfig's current usage, aligned to 4-byte sizes, to deal with LTO and EEPROM page sizing
+# endif
+#endif
+
+#if STM32_ONBOARD_EEPROM_SIZE > 128
+# pragma message("Please note: resetting EEPROM using an STM32L0/L1 device takes up to 1 second for every 1kB of internal EEPROM used.")
+#endif
diff --git a/platforms/chibios/drivers/i2c_master.c b/platforms/chibios/drivers/i2c_master.c
new file mode 100644
index 0000000000..fc4bb2ab37
--- /dev/null
+++ b/platforms/chibios/drivers/i2c_master.c
@@ -0,0 +1,121 @@
+/* Copyright 2018 Jack Humbert
+ * Copyright 2018 Yiancar
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* This library is only valid for STM32 processors.
+ * This library follows the convention of the AVR i2c_master library.
+ * As a result addresses are expected to be already shifted (addr << 1).
+ * I2CD1 is the default driver which corresponds to pins B6 and B7. This
+ * can be changed.
+ * Please ensure that HAL_USE_I2C is TRUE in the halconf.h file and that
+ * STM32_I2C_USE_I2C1 is TRUE in the mcuconf.h file. Pins B6 and B7 are used
+ * but using any other I2C pins should be trivial.
+ */
+#include "quantum.h"
+#include "i2c_master.h"
+#include <string.h>
+#include <hal.h>
+
+static uint8_t i2c_address;
+
+static const I2CConfig i2cconfig = {
+#if defined(USE_I2CV1_CONTRIB)
+ I2C1_CLOCK_SPEED,
+#elif defined(USE_I2CV1)
+ I2C1_OPMODE,
+ I2C1_CLOCK_SPEED,
+ I2C1_DUTY_CYCLE,
+#else
+ // This configures the I2C clock to 400khz assuming a 72Mhz clock
+ // For more info : https://www.st.com/en/embedded-software/stsw-stm32126.html
+ STM32_TIMINGR_PRESC(I2C1_TIMINGR_PRESC) | STM32_TIMINGR_SCLDEL(I2C1_TIMINGR_SCLDEL) | STM32_TIMINGR_SDADEL(I2C1_TIMINGR_SDADEL) | STM32_TIMINGR_SCLH(I2C1_TIMINGR_SCLH) | STM32_TIMINGR_SCLL(I2C1_TIMINGR_SCLL), 0, 0
+#endif
+};
+
+static i2c_status_t chibios_to_qmk(const msg_t* status) {
+ switch (*status) {
+ case I2C_NO_ERROR:
+ return I2C_STATUS_SUCCESS;
+ case I2C_TIMEOUT:
+ return I2C_STATUS_TIMEOUT;
+ // I2C_BUS_ERROR, I2C_ARBITRATION_LOST, I2C_ACK_FAILURE, I2C_OVERRUN, I2C_PEC_ERROR, I2C_SMB_ALERT
+ default:
+ return I2C_STATUS_ERROR;
+ }
+}
+
+__attribute__((weak)) void i2c_init(void) {
+ static bool is_initialised = false;
+ if (!is_initialised) {
+ is_initialised = true;
+
+ // Try releasing special pins for a short time
+ palSetPadMode(I2C1_SCL_BANK, I2C1_SCL, PAL_MODE_INPUT);
+ palSetPadMode(I2C1_SDA_BANK, I2C1_SDA, PAL_MODE_INPUT);
+
+ chThdSleepMilliseconds(10);
+#if defined(USE_GPIOV1)
+ palSetPadMode(I2C1_SCL_BANK, I2C1_SCL, I2C1_SCL_PAL_MODE);
+ palSetPadMode(I2C1_SDA_BANK, I2C1_SDA, I2C1_SDA_PAL_MODE);
+#else
+ palSetPadMode(I2C1_SCL_BANK, I2C1_SCL, PAL_MODE_ALTERNATE(I2C1_SCL_PAL_MODE) | PAL_STM32_OTYPE_OPENDRAIN);
+ palSetPadMode(I2C1_SDA_BANK, I2C1_SDA, PAL_MODE_ALTERNATE(I2C1_SDA_PAL_MODE) | PAL_STM32_OTYPE_OPENDRAIN);
+#endif
+ }
+}
+
+i2c_status_t i2c_start(uint8_t address) {
+ i2c_address = address;
+ i2cStart(&I2C_DRIVER, &i2cconfig);
+ return I2C_STATUS_SUCCESS;
+}
+
+i2c_status_t i2c_transmit(uint8_t address, const uint8_t* data, uint16_t length, uint16_t timeout) {
+ i2c_address = address;
+ i2cStart(&I2C_DRIVER, &i2cconfig);
+ msg_t status = i2cMasterTransmitTimeout(&I2C_DRIVER, (i2c_address >> 1), data, length, 0, 0, TIME_MS2I(timeout));
+ return chibios_to_qmk(&status);
+}
+
+i2c_status_t i2c_receive(uint8_t address, uint8_t* data, uint16_t length, uint16_t timeout) {
+ i2c_address = address;
+ i2cStart(&I2C_DRIVER, &i2cconfig);
+ msg_t status = i2cMasterReceiveTimeout(&I2C_DRIVER, (i2c_address >> 1), data, length, TIME_MS2I(timeout));
+ return chibios_to_qmk(&status);
+}
+
+i2c_status_t i2c_writeReg(uint8_t devaddr, uint8_t regaddr, const uint8_t* data, uint16_t length, uint16_t timeout) {
+ i2c_address = devaddr;
+ i2cStart(&I2C_DRIVER, &i2cconfig);
+
+ uint8_t complete_packet[length + 1];
+ for (uint8_t i = 0; i < length; i++) {
+ complete_packet[i + 1] = data[i];
+ }
+ complete_packet[0] = regaddr;
+
+ msg_t status = i2cMasterTransmitTimeout(&I2C_DRIVER, (i2c_address >> 1), complete_packet, length + 1, 0, 0, TIME_MS2I(timeout));
+ return chibios_to_qmk(&status);
+}
+
+i2c_status_t i2c_readReg(uint8_t devaddr, uint8_t regaddr, uint8_t* data, uint16_t length, uint16_t timeout) {
+ i2c_address = devaddr;
+ i2cStart(&I2C_DRIVER, &i2cconfig);
+ msg_t status = i2cMasterTransmitTimeout(&I2C_DRIVER, (i2c_address >> 1), &regaddr, 1, data, length, TIME_MS2I(timeout));
+ return chibios_to_qmk(&status);
+}
+
+void i2c_stop(void) { i2cStop(&I2C_DRIVER); }
diff --git a/platforms/chibios/drivers/i2c_master.h b/platforms/chibios/drivers/i2c_master.h
new file mode 100644
index 0000000000..c68109acbd
--- /dev/null
+++ b/platforms/chibios/drivers/i2c_master.h
@@ -0,0 +1,113 @@
+/* Copyright 2018 Jack Humbert
+ * Copyright 2018 Yiancar
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* This library follows the convention of the AVR i2c_master library.
+ * As a result addresses are expected to be already shifted (addr << 1).
+ * I2CD1 is the default driver which corresponds to pins B6 and B7. This
+ * can be changed.
+ * Please ensure that HAL_USE_I2C is TRUE in the halconf.h file and that
+ * STM32_I2C_USE_I2C1 is TRUE in the mcuconf.h file.
+ */
+#pragma once
+
+#include <ch.h>
+#include <hal.h>
+
+#ifdef I2C1_BANK
+# define I2C1_SCL_BANK I2C1_BANK
+# define I2C1_SDA_BANK I2C1_BANK
+#endif
+
+#ifndef I2C1_SCL_BANK
+# define I2C1_SCL_BANK GPIOB
+#endif
+
+#ifndef I2C1_SDA_BANK
+# define I2C1_SDA_BANK GPIOB
+#endif
+
+#ifndef I2C1_SCL
+# define I2C1_SCL 6
+#endif
+#ifndef I2C1_SDA
+# define I2C1_SDA 7
+#endif
+
+#ifdef USE_I2CV1
+# ifndef I2C1_OPMODE
+# define I2C1_OPMODE OPMODE_I2C
+# endif
+# ifndef I2C1_CLOCK_SPEED
+# define I2C1_CLOCK_SPEED 100000 /* 400000 */
+# endif
+# ifndef I2C1_DUTY_CYCLE
+# define I2C1_DUTY_CYCLE STD_DUTY_CYCLE /* FAST_DUTY_CYCLE_2 */
+# endif
+#else
+// The default timing values below configures the I2C clock to 400khz assuming a 72Mhz clock
+// For more info : https://www.st.com/en/embedded-software/stsw-stm32126.html
+# ifndef I2C1_TIMINGR_PRESC
+# define I2C1_TIMINGR_PRESC 0U
+# endif
+# ifndef I2C1_TIMINGR_SCLDEL
+# define I2C1_TIMINGR_SCLDEL 7U
+# endif
+# ifndef I2C1_TIMINGR_SDADEL
+# define I2C1_TIMINGR_SDADEL 0U
+# endif
+# ifndef I2C1_TIMINGR_SCLH
+# define I2C1_TIMINGR_SCLH 38U
+# endif
+# ifndef I2C1_TIMINGR_SCLL
+# define I2C1_TIMINGR_SCLL 129U
+# endif
+#endif
+
+#ifndef I2C_DRIVER
+# define I2C_DRIVER I2CD1
+#endif
+
+#ifdef USE_GPIOV1
+# ifndef I2C1_SCL_PAL_MODE
+# define I2C1_SCL_PAL_MODE PAL_MODE_STM32_ALTERNATE_OPENDRAIN
+# endif
+# ifndef I2C1_SDA_PAL_MODE
+# define I2C1_SDA_PAL_MODE PAL_MODE_STM32_ALTERNATE_OPENDRAIN
+# endif
+#else
+// The default PAL alternate modes are used to signal that the pins are used for I2C
+# ifndef I2C1_SCL_PAL_MODE
+# define I2C1_SCL_PAL_MODE 4
+# endif
+# ifndef I2C1_SDA_PAL_MODE
+# define I2C1_SDA_PAL_MODE 4
+# endif
+#endif
+
+typedef int16_t i2c_status_t;
+
+#define I2C_STATUS_SUCCESS (0)
+#define I2C_STATUS_ERROR (-1)
+#define I2C_STATUS_TIMEOUT (-2)
+
+void i2c_init(void);
+i2c_status_t i2c_start(uint8_t address);
+i2c_status_t i2c_transmit(uint8_t address, const uint8_t* data, uint16_t length, uint16_t timeout);
+i2c_status_t i2c_receive(uint8_t address, uint8_t* data, uint16_t length, uint16_t timeout);
+i2c_status_t i2c_writeReg(uint8_t devaddr, uint8_t regaddr, const uint8_t* data, uint16_t length, uint16_t timeout);
+i2c_status_t i2c_readReg(uint8_t devaddr, uint8_t regaddr, uint8_t* data, uint16_t length, uint16_t timeout);
+void i2c_stop(void);
diff --git a/platforms/chibios/drivers/serial.c b/platforms/chibios/drivers/serial.c
new file mode 100644
index 0000000000..f54fbcee4e
--- /dev/null
+++ b/platforms/chibios/drivers/serial.c
@@ -0,0 +1,278 @@
+/*
+ * WARNING: be careful changing this code, it is very timing dependent
+ */
+
+#include "quantum.h"
+#include "serial.h"
+#include "wait.h"
+
+#include <hal.h>
+
+// TODO: resolve/remove build warnings
+#if defined(RGBLIGHT_ENABLE) && defined(RGBLED_SPLIT) && defined(PROTOCOL_CHIBIOS) && defined(WS2812_DRIVER_BITBANG)
+# warning "RGBLED_SPLIT not supported with bitbang WS2812 driver"
+#endif
+
+// default wait implementation cannot be called within interrupt
+// this method seems to be more accurate than GPT timers
+#if PORT_SUPPORTS_RT == FALSE
+# error "chSysPolledDelayX method not supported on this platform"
+#else
+# undef wait_us
+# define wait_us(x) chSysPolledDelayX(US2RTC(STM32_SYSCLK, x))
+#endif
+
+#ifndef SELECT_SOFT_SERIAL_SPEED
+# define SELECT_SOFT_SERIAL_SPEED 1
+// TODO: correct speeds...
+// 0: about 189kbps (Experimental only)
+// 1: about 137kbps (default)
+// 2: about 75kbps
+// 3: about 39kbps
+// 4: about 26kbps
+// 5: about 20kbps
+#endif
+
+// Serial pulse period in microseconds. At the moment, going lower than 12 causes communication failure
+#if SELECT_SOFT_SERIAL_SPEED == 0
+# define SERIAL_DELAY 12
+#elif SELECT_SOFT_SERIAL_SPEED == 1
+# define SERIAL_DELAY 16
+#elif SELECT_SOFT_SERIAL_SPEED == 2
+# define SERIAL_DELAY 24
+#elif SELECT_SOFT_SERIAL_SPEED == 3
+# define SERIAL_DELAY 32
+#elif SELECT_SOFT_SERIAL_SPEED == 4
+# define SERIAL_DELAY 48
+#elif SELECT_SOFT_SERIAL_SPEED == 5
+# define SERIAL_DELAY 64
+#else
+# error invalid SELECT_SOFT_SERIAL_SPEED value
+#endif
+
+inline static void serial_delay(void) { wait_us(SERIAL_DELAY); }
+inline static void serial_delay_half(void) { wait_us(SERIAL_DELAY / 2); }
+inline static void serial_delay_blip(void) { wait_us(1); }
+inline static void serial_output(void) { setPinOutput(SOFT_SERIAL_PIN); }
+inline static void serial_input(void) { setPinInputHigh(SOFT_SERIAL_PIN); }
+inline static bool serial_read_pin(void) { return !!readPin(SOFT_SERIAL_PIN); }
+inline static void serial_low(void) { writePinLow(SOFT_SERIAL_PIN); }
+inline static void serial_high(void) { writePinHigh(SOFT_SERIAL_PIN); }
+
+void interrupt_handler(void *arg);
+
+// Use thread + palWaitLineTimeout instead of palSetLineCallback
+// - Methods like setPinOutput and palEnableLineEvent/palDisableLineEvent
+// cause the interrupt to lock up, which would limit to only receiving data...
+static THD_WORKING_AREA(waThread1, 128);
+static THD_FUNCTION(Thread1, arg) {
+ (void)arg;
+ chRegSetThreadName("blinker");
+ while (true) {
+ palWaitLineTimeout(SOFT_SERIAL_PIN, TIME_INFINITE);
+ interrupt_handler(NULL);
+ }
+}
+
+void soft_serial_initiator_init(void) {
+ serial_output();
+ serial_high();
+}
+
+void soft_serial_target_init(void) {
+ serial_input();
+
+ palEnablePadEvent(PAL_PORT(SOFT_SERIAL_PIN), PAL_PAD(SOFT_SERIAL_PIN), PAL_EVENT_MODE_FALL