diff options
Diffstat (limited to 'drivers')
24 files changed, 2201 insertions, 1 deletions
diff --git a/drivers/gpio/sn74x154.c b/drivers/gpio/sn74x154.c new file mode 100644 index 0000000000..5f21f12b55 --- /dev/null +++ b/drivers/gpio/sn74x154.c @@ -0,0 +1,58 @@ +/* Copyright 2022 + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "sn74x154.h" +#include "gpio.h" + +#define ADDRESS_PIN_COUNT 4 + +#ifndef SN74X154_ADDRESS_PINS +# error sn74x154: no address pins defined! +#endif + +static const pin_t address_pins[ADDRESS_PIN_COUNT] = SN74X154_ADDRESS_PINS; + +void sn74x154_init(void) { + for (int i = 0; i < ADDRESS_PIN_COUNT; i++) { + setPinOutput(address_pins[i]); + writePinLow(address_pins[i]); + } + +#if defined(SN74X154_E0_PIN) + setPinOutput(SN74X154_E0_PIN); + writePinHigh(SN74X154_E0_PIN); +#endif + +#if defined(SN74X154_E1_PIN) + setPinOutput(SN74X154_E1_PIN); + writePinHigh(SN74X154_E1_PIN); +#endif +} + +void sn74x154_set_enabled(bool enabled) { +#if defined(SN74X154_E0_PIN) + writePin(SN74X154_E0_PIN, !enabled); +#endif +#if defined(SN74X154_E1_PIN) + writePin(SN74X154_E1_PIN, !enabled); +#endif +} + +void sn74x154_set_addr(uint8_t address) { + for (int i = 0; i < ADDRESS_PIN_COUNT; i++) { + writePin(address_pins[i], address & (1 << i)); + } +} diff --git a/drivers/gpio/sn74x154.h b/drivers/gpio/sn74x154.h new file mode 100644 index 0000000000..ce6a9ddb0e --- /dev/null +++ b/drivers/gpio/sn74x154.h @@ -0,0 +1,48 @@ +/* Copyright 2022 + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#pragma once + +#include <stdint.h> +#include <stdbool.h> + +/** + * Driver for 74x154 4-to-16 decoder/demultiplexer with inverting outputs + * https://assets.nexperia.com/documents/data-sheet/74HC_HCT154.pdf + */ + +/** + * Initialize the address and output enable pins. + */ +void sn74x154_init(void); + +/** + * Set the enabled state. + * + * When enabled is true, pulls the E0 and E1 pins low. + * + * \param enabled The enable state to set. + */ +void sn74x154_set_enabled(bool enabled); + +/** + * Set the output pin address. + * + * The selected output pin will be pulled low, while the remaining output pins will be high. + * + * \param address The address to set, from 0 to 15. + */ +void sn74x154_set_addr(uint8_t address); diff --git a/drivers/lcd/hd44780.c b/drivers/lcd/hd44780.c new file mode 100644 index 0000000000..c988ebe56c --- /dev/null +++ b/drivers/lcd/hd44780.c @@ -0,0 +1,284 @@ +/* +Copyright 2022 + +This program is free software: you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation, either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#include "hd44780.h" +#include "gpio.h" +#include "progmem.h" +#include "wait.h" + +#ifndef HD44780_DATA_PINS +# error hd44780: no data pins defined! +#endif + +#ifndef HD44780_RS_PIN +# error hd44780: no RS pin defined! +#endif + +#ifndef HD44780_RW_PIN +# error hd44780: no R/W pin defined! +#endif + +#ifndef HD44780_E_PIN +# error hd44780: no E pin defined! +#endif + +static const pin_t data_pins[4] = HD44780_DATA_PINS; + +#ifndef HD44780_DISPLAY_COLS +# define HD44780_DISPLAY_COLS 16 +#endif + +#ifndef HD44780_DISPLAY_LINES +# define HD44780_DISPLAY_LINES 2 +#endif + +#ifndef HD44780_DDRAM_LINE0_ADDR +# define HD44780_DDRAM_LINE0_ADDR 0x00 +#endif +#ifndef HD44780_DDRAM_LINE1_ADDR +# define HD44780_DDRAM_LINE1_ADDR 0x40 +#endif + +#define HD44780_INIT_DELAY_MS 16 +#define HD44780_ENABLE_DELAY_US 1 + +static void hd44780_latch(void) { + writePinHigh(HD44780_E_PIN); + wait_us(HD44780_ENABLE_DELAY_US); + writePinLow(HD44780_E_PIN); +} + +void hd44780_write(uint8_t data, bool isData) { + writePin(HD44780_RS_PIN, isData); + writePinLow(HD44780_RW_PIN); + + for (int i = 0; i < 4; i++) { + setPinOutput(data_pins[i]); + } + + // Write high nibble + for (int i = 0; i < 4; i++) { + writePin(data_pins[i], (data >> 4) & (1 << i)); + } + hd44780_latch(); + + // Write low nibble + for (int i = 0; i < 4; i++) { + writePin(data_pins[i], data & (1 << i)); + } + hd44780_latch(); + + for (int i = 0; i < 4; i++) { + writePinHigh(data_pins[i]); + } +} + +uint8_t hd44780_read(bool isData) { + uint8_t data = 0; + + writePin(HD44780_RS_PIN, isData); + writePinHigh(HD44780_RW_PIN); + + for (int i = 0; i < 4; i++) { + setPinInput(data_pins[i]); + } + + writePinHigh(HD44780_E_PIN); + wait_us(HD44780_ENABLE_DELAY_US); + + // Read high nibble + for (int i = 0; i < 4; i++) { + data |= (readPin(data_pins[i]) << i); + } + + data <<= 4; + + writePinLow(HD44780_E_PIN); + wait_us(HD44780_ENABLE_DELAY_US); + writePinHigh(HD44780_E_PIN); + wait_us(HD44780_ENABLE_DELAY_US); + + // Read low nibble + for (int i = 0; i < 4; i++) { + data |= (readPin(data_pins[i]) << i); + } + + writePinLow(HD44780_E_PIN); + + return data; +} + +bool hd44780_busy(void) { + return hd44780_read(false) & HD44780_BUSY_FLAG; +} + +void hd44780_command(uint8_t command) { + while (hd44780_busy()) + ; + hd44780_write(command, false); +} + +void hd44780_data(uint8_t data) { + while (hd44780_busy()) + ; + hd44780_write(data, true); +} + +void hd44780_clear(void) { + hd44780_command(HD44780_CMD_CLEAR_DISPLAY); +} + +void hd44780_home(void) { + hd44780_command(HD44780_CMD_RETURN_HOME); +} + +void hd44780_on(bool cursor, bool blink) { + if (cursor) { + if (blink) { + hd44780_command(HD44780_CMD_DISPLAY | HD44780_DISPLAY_ON | HD44780_DISPLAY_CURSOR | HD44780_DISPLAY_BLINK); + } else { + hd44780_command(HD44780_CMD_DISPLAY | HD44780_DISPLAY_ON | HD44780_DISPLAY_CURSOR); + } + } else { + hd44780_command(HD44780_CMD_DISPLAY | HD44780_DISPLAY_ON); + } +} + +void hd44780_off() { + hd44780_command(HD44780_CMD_DISPLAY); +} + +void hd44780_set_cgram_address(uint8_t address) { + hd44780_command(HD44780_CMD_SET_CGRAM_ADDRESS + (address & 0x3F)); +} + +void hd44780_set_ddram_address(uint8_t address) { + hd44780_command(HD44780_CMD_SET_DDRAM_ADDRESS + (address & 0x7F)); +} + +void hd44780_init(bool cursor, bool blink) { + setPinOutput(HD44780_RS_PIN); + setPinOutput(HD44780_RW_PIN); + setPinOutput(HD44780_E_PIN); + + for (int i = 0; i < 4; i++) { + setPinOutput(data_pins[i]); + } + + wait_ms(HD44780_INIT_DELAY_MS); + + // Manually configure for 4-bit mode - can't use hd44780_command() yet + // HD44780U datasheet, Fig. 24 (p46) + writePinHigh(data_pins[0]); // Function set + writePinHigh(data_pins[1]); // DL = 1 + hd44780_latch(); + wait_ms(5); + // Send again + hd44780_latch(); + wait_us(64); + // And again (?) + hd44780_latch(); + wait_us(64); + + writePinLow(data_pins[0]); // DL = 0 + hd44780_latch(); + wait_us(64); + +#if HD44780_DISPLAY_LINES == 1 + hd44780_command(HD44780_CMD_FUNCTION); // 4 bit, 1 line, 5x8 dots +#else + hd44780_command(HD44780_CMD_FUNCTION | HD44780_FUNCTION_2_LINES); // 4 bit, 2 lines, 5x8 dots +#endif + hd44780_on(cursor, blink); + hd44780_clear(); + hd44780_home(); + hd44780_command(HD44780_CMD_ENTRY_MODE | HD44780_ENTRY_MODE_INC); +} + +void hd44780_set_cursor(uint8_t col, uint8_t line) { + register uint8_t address = col; + +#if HD44780_DISPLAY_LINES == 1 + address += HD44780_DDRAM_LINE0_ADDR; +#elif HD44780_DISPLAY_LINES == 2 + if (line == 0) { + address += HD44780_DDRAM_LINE0_ADDR; + } else { + address += HD44780_DDRAM_LINE1_ADDR; + } +#endif + + hd44780_set_ddram_address(address); +} + +void hd44780_define_char(uint8_t index, uint8_t *data) { + hd44780_set_cgram_address((index & 0x7) << 3); + for (uint8_t i = 0; i < 8; i++) { + hd44780_data(data[i]); + } +} + +void hd44780_putc(char c) { + while (hd44780_busy()) + ; + uint8_t current_position = hd44780_read(false); + + if (c == '\n') { + hd44780_set_cursor(0, current_position < HD44780_DDRAM_LINE1_ADDR ? 1 : 0); + } else { +#if defined(HD44780_WRAP_LINES) +# if HD44780_DISPLAY_LINES == 1 + if (current_position == HD44780_DDRAM_LINE0_ADDR + HD44780_DISPLAY_COLS) { + // Go to start of line + hd44780_set_cursor(0, 0); + } +# elif HD44780_DISPLAY_LINES == 2 + if (current_position == HD44780_DDRAM_LINE0_ADDR + HD44780_DISPLAY_COLS) { + // Go to start of second line + hd44780_set_cursor(0, 1); + } else if (current_position == HD44780_DDRAM_LINE1_ADDR + HD44780_DISPLAY_COLS) { + // Go to start of first line + hd44780_set_cursor(0, 0); + } +# endif +#endif + hd44780_data(c); + } +} + +void hd44780_puts(const char *s) { + register char c; + while ((c = *s++)) { + hd44780_putc(c); + } +} + +#if defined(__AVR__) +void hd44780_define_char_P(uint8_t index, const uint8_t *data) { + hd44780_set_cgram_address(index << 3); + for (uint8_t i = 0; i < 8; i++) { + hd44780_data(pgm_read_byte(data++)); + } +} + +void hd44780_puts_P(const char *s) { + register char c; + while ((c = pgm_read_byte(s++))) { + hd44780_putc(c); + } +} +#endif diff --git a/drivers/lcd/hd44780.h b/drivers/lcd/hd44780.h new file mode 100644 index 0000000000..9e43339344 --- /dev/null +++ b/drivers/lcd/hd44780.h @@ -0,0 +1,220 @@ +/* +Copyright 2022 + +This program is free software: you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation, either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#pragma once + +#include <stdint.h> +#include <stdbool.h> + +/** + * \defgroup hd44780 + * + * HD44780 Character LCD Driver + * \{ + */ + +/* + * HD44780 instructions + * https://www.sparkfun.com/datasheets/LCD/HD44780.pdf + * Table 6 (p24) + */ +// Clear display +#define HD44780_CMD_CLEAR_DISPLAY 0x01 +// Return home +#define HD44780_CMD_RETURN_HOME 0x02 +// Entry mode set +#define HD44780_CMD_ENTRY_MODE 0x04 +#define HD44780_ENTRY_MODE_INC 0x02 // I/D +#define HD44780_ENTRY_MODE_SHIFT 0x01 // S +// Display on/off control +#define HD44780_CMD_DISPLAY 0x08 +#define HD44780_DISPLAY_ON 0x04 // D +#define HD44780_DISPLAY_CURSOR 0x02 // C +#define HD44780_DISPLAY_BLINK 0x01 // B +// Cursor or display shift +#define HD44780_CMD_MOVE 0x10 +#define HD44780_MOVE_DISPLAY 0x08 // S/C +#define HD44780_MOVE_RIGHT 0x04 // R/L +// Function set +#define HD44780_CMD_FUNCTION 0x20 +#define HD44780_FUNCTION_8_BIT 0x10 // DL +#define HD44780_FUNCTION_2_LINES 0x08 // N +#define HD44780_FUNCTION_5X10_DOTS 0x04 // F +// Set CGRAM address +#define HD44780_CMD_SET_CGRAM_ADDRESS 0x40 +// Set DDRAM address +#define HD44780_CMD_SET_DDRAM_ADDRESS 0x80 + +// Bitmask for busy flag when reading +#define HD44780_BUSY_FLAG 0x80 + +/** + * \brief Write a byte to the display. + * + * \param data The byte to send to the display. + * \param isData Whether the byte is an instruction or character data. + */ +void hd44780_write(uint8_t data, bool isData); + +/** + * \brief Read a byte from the display. + * + * \param isData Whether to read the current cursor position, or the character at the cursor. + * + * \return If `isData` is `true`, the returned byte will be the character at the current DDRAM address. Otherwise, it will be the current DDRAM address and the busy flag. + */ +uint8_t hd44780_read(bool isData); + +/** + * \brief Indicates whether the display is currently processing, and cannot accept instructions. + * + * \return `true` if the display is busy. + */ +bool hd44780_busy(void); + +/** + * \brief Send a command to the display. Refer to the datasheet for the valid commands. + * + * This function waits for the display to clear the busy flag before sending the command. + * + * \param command The command to send. + */ +void hd44780_command(uint8_t command); + +/** + * \brief Send a byte of data to the display. + * + * This function waits for the display to clear the busy flag before sending the data. + * + * \param data The byte of data to send. + */ +void hd44780_data(uint8_t data); + +/** + * \brief Clear the display. + * + * This function is called on init. + */ +void hd44780_clear(void); + +/** + * \brief Move the cursor to the home position. + * + * This function is called on init. + */ +void hd44780_home(void); + +/** + * \brief Turn the display on, and/or set the cursor position. + * + * This function is called on init. + * + * \param cursor Whether to show the cursor. + * \param blink Whether to blink the cursor, if shown. + */ +void hd44780_on(bool cursor, bool blink); + +/** + * \brief Turn the display off. + */ +void hd44780_off(void); + +/** + * \brief Set the CGRAM address. + * + * This function is used when defining custom characters. + * + * \param address The CGRAM address to move to, from `0x00` to `0x3F`. + */ +void hd44780_set_cgram_address(uint8_t address); + +/** + * \brief Set the DDRAM address. + * + * This function is used when printing characters to the display, and setting the cursor. + * + * \param address The DDRAM address to move to, from `0x00` to `0x7F`. + */ +void hd44780_set_ddram_address(uint8_t address); + +/** + * \brief Initialize the display. + * + * This function should be called only once, before any of the other functions can be called. + * + * \param cursor Whether to show the cursor. + * \param blink Whether to blink the cursor, if shown. + */ +void hd44780_init(bool cursor, bool blink); + +/** + * \brief Move the cursor to the specified position on the display. + * + * \param col The column number to move to, from 0 to 15 on 16x2 displays. + * \param line The line number to move to, either 0 or 1 on 16x2 displays. + */ +void hd44780_set_cursor(uint8_t col, uint8_t line); + +/** + * \brief Define a custom character. + * + * \param index The index of the custom character to define, from 0 to 7. + * \param data An array of 8 bytes containing the 5-bit row data of the character, where the first byte is the topmost row, and the least significant bit of each byte is the rightmost column. + */ +void hd44780_define_char(uint8_t index, uint8_t *data); + +/** + * \brief Print a character to the display. The newline character will move the cursor to the start of the next line. + * + * The exact character shown may depend on the ROM code of your particular display - refer to the datasheet for the full character set. + * + * \param c The character to print. + */ +void hd44780_putc(char c); + +/** + * \brief Print a string of characters to the display. + * + * \param s The string to print. + */ +void hd44780_puts(const char *s); + +#if defined(__AVR__) || defined(__DOXYGEN__) +/** + * \brief Define a custom character from PROGMEM. + * + * On ARM devices, this function is simply an alias of hd44780_define_char(). + * + * \param index The index of the custom character to define, from 0 to 7. + * \param data A PROGMEM array of 8 bytes containing the 5-bit row data of the character, where the first byte is the topmost row, and the least significant bit of each byte is the rightmost column. + */ +void hd44780_define_char_P(uint8_t index, const uint8_t *data); + +/** + * \brief Print a string of characters from PROGMEM to the display. + * + * On ARM devices, this function is simply an alias of hd44780_puts(). + * + * \param s The PROGMEM string to print. + */ +void hd44780_puts_P(const char *s); +#else +# define hd44780_define_char_P(index, data) hd44780_define_char(index, data) +# define hd44780_puts_P(s) hd44780_puts(s) +#endif + +/** \} */ diff --git a/drivers/led/issi/is31fl3737.c b/drivers/led/issi/is31fl3737.c index 9f2a13de45..bce0c34b2c 100644 --- a/drivers/led/issi/is31fl3737.c +++ b/drivers/led/issi/is31fl3737.c @@ -57,6 +57,10 @@ # define ISSI_PERSISTENCE 0 #endif +#ifndef ISSI_PWM_FREQUENCY +# define ISSI_PWM_FREQUENCY 0b000 // PFS - IS31FL3737B only +#endif + #ifndef ISSI_SWPULLUP # define ISSI_SWPULLUP PUR_0R #endif @@ -159,7 +163,7 @@ void IS31FL3737_init(uint8_t addr) { // Set global current to maximum. IS31FL3737_write_register(addr, ISSI_REG_GLOBALCURRENT, 0xFF); // Disable software shutdown. - IS31FL3737_write_register(addr, ISSI_REG_CONFIGURATION, 0x01); + IS31FL3737_write_register(addr, ISSI_REG_CONFIGURATION, ((ISSI_PWM_FREQUENCY & 0b111) << 3) | 0x01); // Wait 10ms to ensure the device has woken up. wait_ms(10); diff --git a/drivers/painter/comms/qp_comms_spi.c b/drivers/painter/comms/qp_comms_spi.c new file mode 100644 index 0000000000..e644ba9f84 --- /dev/null +++ b/drivers/painter/comms/qp_comms_spi.c @@ -0,0 +1,137 @@ +// Copyright 2021 Nick Brassel (@tzarc) +// SPDX-License-Identifier: GPL-2.0-or-later + +#ifdef QUANTUM_PAINTER_SPI_ENABLE + +# include "spi_master.h" +# include "qp_comms_spi.h" + +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// Base SPI support + +bool qp_comms_spi_init(painter_device_t device) { + struct painter_driver_t * driver = (struct painter_driver_t *)device; + struct qp_comms_spi_config_t *comms_config = (struct qp_comms_spi_config_t *)driver->comms_config; + + // Initialize the SPI peripheral + spi_init(); + + // Set up CS as output high + setPinOutput(comms_config->chip_select_pin); + writePinHigh(comms_config->chip_select_pin); + + return true; +} + +bool qp_comms_spi_start(painter_device_t device) { + struct painter_driver_t * driver = (struct painter_driver_t *)device; + struct qp_comms_spi_config_t *comms_config = (struct qp_comms_spi_config_t *)driver->comms_config; + + return spi_start(comms_config->chip_select_pin, comms_config->lsb_first, comms_config->mode, comms_config->divisor); +} + +uint32_t qp_comms_spi_send_data(painter_device_t device, const void *data, uint32_t byte_count) { + uint32_t bytes_remaining = byte_count; + const uint8_t *p = (const uint8_t *)data; + while (bytes_remaining > 0) { + uint32_t bytes_this_loop = bytes_remaining < 1024 ? bytes_remaining : 1024; + spi_transmit(p, bytes_this_loop); + p += bytes_this_loop; + bytes_remaining -= bytes_this_loop; + } + + return byte_count - bytes_remaining; +} + +void qp_comms_spi_stop(painter_device_t device) { + struct painter_driver_t * driver = (struct painter_driver_t *)device; + struct qp_comms_spi_config_t *comms_config = (struct qp_comms_spi_config_t *)driver->comms_config; + spi_stop(); + writePinHigh(comms_config->chip_select_pin); +} + +const struct painter_comms_vtable_t spi_comms_vtable = { + .comms_init = qp_comms_spi_init, + .comms_start = qp_comms_spi_start, + .comms_send = qp_comms_spi_send_data, + .comms_stop = qp_comms_spi_stop, +}; + +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// SPI with D/C and RST pins + +# ifdef QUANTUM_PAINTER_SPI_DC_RESET_ENABLE + +bool qp_comms_spi_dc_reset_init(painter_device_t device) { + if (!qp_comms_spi_init(device)) { + return false; + } + + struct painter_driver_t * driver = (struct painter_driver_t *)device; + struct qp_comms_spi_dc_reset_config_t *comms_config = (struct qp_comms_spi_dc_reset_config_t *)driver->comms_config; + + // Set up D/C as output low, if specified + if (comms_config->dc_pin != NO_PIN) { + setPinOutput(comms_config->dc_pin); + writePinLow(comms_config->dc_pin); + } + + // Set up RST as output, if specified, performing a reset in the process + if (comms_config->reset_pin != NO_PIN) { + setPinOutput(comms_config->reset_pin); + writePinLow(comms_config->reset_pin); + wait_ms(20); + writePinHigh(comms_config->reset_pin); + wait_ms(20); + } + + return true; +} + +uint32_t qp_comms_spi_dc_reset_send_data(painter_device_t device, const void *data, uint32_t byte_count) { + struct painter_driver_t * driver = (struct painter_driver_t *)device; + struct qp_comms_spi_dc_reset_config_t *comms_config = (struct qp_comms_spi_dc_reset_config_t *)driver->comms_config; + writePinHigh(comms_config->dc_pin); + return qp_comms_spi_send_data(device, data, byte_count); +} + +void qp_comms_spi_dc_reset_send_command(painter_device_t device, uint8_t cmd) { + struct painter_driver_t * driver = (struct painter_driver_t *)device; + struct qp_comms_spi_dc_reset_config_t *comms_config = (struct qp_comms_spi_dc_reset_config_t *)driver->comms_config; + writePinLow(comms_config->dc_pin); + spi_write(cmd); +} + +void qp_comms_spi_dc_reset_bulk_command_sequence(painter_device_t device, const uint8_t *sequence, size_t sequence_len) { + for (size_t i = 0; i < sequence_len;) { + uint8_t command = sequence[i]; + uint8_t delay = sequence[i + 1]; + uint8_t num_bytes = sequence[i + 2]; + qp_comms_spi_dc_reset_send_command(device, command); + if (num_bytes > 0) { + qp_comms_spi_dc_reset_send_data(device, &sequence[i + 3], num_bytes); + } + if (delay > 0) { + wait_ms(delay); + } + i += (3 + num_bytes); + } +} + +const struct painter_comms_with_command_vtable_t spi_comms_with_dc_vtable = { + .base = + { + .comms_init = qp_comms_spi_dc_reset_init, + .comms_start = qp_comms_spi_start, + .comms_send = qp_comms_spi_dc_reset_send_data, + .comms_stop = qp_comms_spi_stop, + }, + .send_command = qp_comms_spi_dc_reset_send_command, + .bulk_command_sequence = qp_comms_spi_dc_reset_bulk_command_sequence, +}; + +# endif // QUANTUM_PAINTER_SPI_DC_RESET_ENABLE + +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +#endif // QUANTUM_PAINTER_SPI_ENABLE diff --git a/drivers/painter/comms/qp_comms_spi.h b/drivers/painter/comms/qp_comms_spi.h new file mode 100644 index 0000000000..9989987327 --- /dev/null +++ b/drivers/painter/comms/qp_comms_spi.h @@ -0,0 +1,51 @@ +// Copyright 2021 Nick Brassel (@tzarc) +// SPDX-License-Identifier: GPL-2.0-or-later + +#pragma once + +#ifdef QUANTUM_PAINTER_SPI_ENABLE + +# include <stdint.h> + +# include "gpio.h" +# include "qp_internal.h" + +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// Base SPI support + +struct qp_comms_spi_config_t { + pin_t chip_select_pin; + uint16_t divisor; + bool lsb_first; + int8_t mode; +}; + +bool qp_comms_spi_init(painter_device_t device); +bool qp_comms_spi_start(painter_device_t device); +uint32_t qp_comms_spi_send_data(painter_device_t device, const void* data, uint32_t byte_count); +void qp_comms_spi_stop(painter_device_t device); + +extern const struct painter_comms_vtable_t spi_comms_vtable; + +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// SPI with D/C and RST pins + +# ifdef QUANTUM_PAINTER_SPI_DC_RESET_ENABLE + +struct qp_comms_spi_dc_reset_config_t { + struct qp_comms_spi_config_t spi_config; + pin_t dc_pin; + pin_t reset_pin; +}; + +void qp_comms_spi_dc_reset_send_command(painter_device_t device, uint8_t cmd); +uint32_t qp_comms_spi_dc_reset_send_data(painter_device_t device, const void* data, uint32_t byte_count); +void qp_comms_spi_dc_reset_bulk_command_sequence(painter_device_t device, const uint8_t* sequence, size_t sequence_len); + +extern const struct painter_comms_with_command_vtable_t spi_comms_with_dc_vtable; + +# endif // QUANTUM_PAINTER_SPI_DC_RESET_ENABLE + +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +#endif // QUANTUM_PAINTER_SPI_ENABLE diff --git a/drivers/painter/gc9a01/qp_gc9a01.c b/drivers/painter/gc9a01/qp_gc9a01.c new file mode 100644 index 0000000000..ad76d58b07 --- /dev/null +++ b/drivers/painter/gc9a01/qp_gc9a01.c @@ -0,0 +1,150 @@ +// Copyright 2021 Paul Cotter (@gr1mr3aver) +// SPDX-License-Identifier: GPL-2.0-or-later + +#include <wait.h> +#include "qp_internal.h" +#include "qp_comms.h" +#include "qp_gc9a01.h" +#include "qp_gc9a01_opcodes.h" +#include "qp_tft_panel.h" + +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// Driver storage +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +tft_panel_dc_reset_painter_device_t gc9a01_drivers[GC9A01_NUM_DEVICES] = {0}; + +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// Initialization +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +bool qp_gc9a01_init(painter_device_t device, painter_rotation_t rotation) { + // A lot of these "unknown" opcodes are sourced from other OSS projects and are seemingly required for this display to function. + // clang-format off + const uint8_t gc9a01_init_sequence[] = { + // Command, Delay, N, Data[N] + GC9A01_SET_INTER_REG_ENABLE2, 0, 0, + 0xEB, 0, 1, 0x14, + GC9A01_SET_INTER_REG_ENABLE1, 0, 0, + GC9A01_SET_INTER_REG_ENABLE2, 0, 0, + 0xEB, 0, 1, 0x14, + 0x84, 0, 1, 0x40, + 0x85, 0, 1, 0xFF, + 0x86, 0, 1, 0xFF, + 0x87, 0, 1, 0xFF, + 0x88, 0, 1, 0x0A, + 0x89, 0, 1, 0x21, + 0x8a, 0, 1, 0x00, + 0x8b, 0, 1, 0x80, + 0x8c, 0, 1, 0x01, + 0x8d, 0, 1, 0x01, + 0x8e, 0, 1, 0xFF, + 0x8f, 0, 1, 0xFF, + GC9A01_SET_FUNCTION_CTL, 0, 2, 0x00, 0x20, |