diff options
Diffstat (limited to 'drivers')
36 files changed, 1610 insertions, 231 deletions
diff --git a/drivers/eeprom/eeprom_i2c.h b/drivers/eeprom/eeprom_i2c.h index 77eea66d63..85317c9ea5 100644 --- a/drivers/eeprom/eeprom_i2c.h +++ b/drivers/eeprom/eeprom_i2c.h @@ -54,6 +54,11 @@ # define EXTERNAL_EEPROM_PAGE_SIZE 32 # define EXTERNAL_EEPROM_ADDRESS_SIZE 2 # define EXTERNAL_EEPROM_WRITE_TIME 5 +#elif defined(EEPROM_I2C_24LC32A) +# define EXTERNAL_EEPROM_BYTE_COUNT 4096 +# define EXTERNAL_EEPROM_PAGE_SIZE 32 +# define EXTERNAL_EEPROM_ADDRESS_SIZE 2 +# define EXTERNAL_EEPROM_WRITE_TIME 5 #elif defined(EEPROM_I2C_MB85RC256V) # define EXTERNAL_EEPROM_BYTE_COUNT 32768 # define EXTERNAL_EEPROM_PAGE_SIZE 128 diff --git a/drivers/eeprom/eeprom_spi.c b/drivers/eeprom/eeprom_spi.c index 25955498c4..51ba25dece 100644 --- a/drivers/eeprom/eeprom_spi.c +++ b/drivers/eeprom/eeprom_spi.c @@ -58,14 +58,20 @@ static bool spi_eeprom_start(void) { static spi_status_t spi_eeprom_wait_while_busy(int timeout) { uint32_t deadline = timer_read32() + timeout; - spi_status_t response; - do { + spi_status_t response = SR_WIP; + while (response & SR_WIP) { + if (!spi_eeprom_start()) { + return SPI_STATUS_ERROR; + } + spi_write(CMD_RDSR); response = spi_read(); + spi_stop(); + if (timer_read32() >= deadline) { return SPI_STATUS_TIMEOUT; } - } while (response & SR_WIP); + } return SPI_STATUS_SUCCESS; } @@ -105,27 +111,21 @@ void eeprom_driver_erase(void) { void eeprom_read_block(void *buf, const void *addr, size_t len) { //------------------------------------------------- // Wait for the write-in-progress bit to be cleared - bool res = spi_eeprom_start(); - if (!res) { - dprint("failed to start SPI for WIP check\n"); - memset(buf, 0, len); - return; - } - spi_status_t response = spi_eeprom_wait_while_busy(EXTERNAL_EEPROM_SPI_TIMEOUT); - spi_stop(); - if (response == SPI_STATUS_TIMEOUT) { - dprint("SPI timeout for WIP check\n"); + if (response != SPI_STATUS_SUCCESS) { + spi_stop(); memset(buf, 0, len); + dprint("SPI timeout for WIP check\n"); return; } //------------------------------------------------- // Perform read - res = spi_eeprom_start(); + bool res = spi_eeprom_start(); if (!res) { - dprint("failed to start SPI for read\n"); + spi_stop(); memset(buf, 0, len); + dprint("failed to start SPI for read\n"); return; } @@ -158,15 +158,9 @@ void eeprom_write_block(const void *buf, void *addr, size_t len) { //------------------------------------------------- // Wait for the write-in-progress bit to be cleared - res = spi_eeprom_start(); - if (!res) { - dprint("failed to start SPI for WIP check\n"); - return; - } - spi_status_t response = spi_eeprom_wait_while_busy(EXTERNAL_EEPROM_SPI_TIMEOUT); - spi_stop(); - if (response == SPI_STATUS_TIMEOUT) { + if (response != SPI_STATUS_SUCCESS) { + spi_stop(); dprint("SPI timeout for WIP check\n"); return; } @@ -175,6 +169,7 @@ void eeprom_write_block(const void *buf, void *addr, size_t len) { // Enable writes res = spi_eeprom_start(); if (!res) { + spi_stop(); dprint("failed to start SPI for write-enable\n"); return; } @@ -186,6 +181,7 @@ void eeprom_write_block(const void *buf, void *addr, size_t len) { // Perform the write res = spi_eeprom_start(); if (!res) { + spi_stop(); dprint("failed to start SPI for write\n"); return; } diff --git a/drivers/eeprom/eeprom_wear_leveling.c b/drivers/eeprom/eeprom_wear_leveling.c new file mode 100644 index 0000000000..bd77eef35c --- /dev/null +++ b/drivers/eeprom/eeprom_wear_leveling.c @@ -0,0 +1,23 @@ +// Copyright 2022 Nick Brassel (@tzarc) +// SPDX-License-Identifier: GPL-2.0-or-later +#include <stdint.h> +#include <string.h> + +#include "eeprom_driver.h" +#include "wear_leveling.h" + +void eeprom_driver_init(void) { + wear_leveling_init(); +} + +void eeprom_driver_erase(void) { + wear_leveling_erase(); +} + +void eeprom_read_block(void *buf, const void *addr, size_t len) { + wear_leveling_read((uint32_t)addr, buf, len); +} + +void eeprom_write_block(const void *buf, void *addr, size_t len) { + wear_leveling_write((uint32_t)addr, buf, len); +} diff --git a/drivers/gpio/pca9505.c b/drivers/gpio/pca9505.c new file mode 100644 index 0000000000..5803746c96 --- /dev/null +++ b/drivers/gpio/pca9505.c @@ -0,0 +1,166 @@ +// Copyright 2022 nirim000 +// SPDX-License-Identifier: GPL-2.0-or-later + +#include "i2c_master.h" +#include "pca9505.h" + +#include "debug.h" + +#define SLAVE_TO_ADDR(n) (n << 1) +#define TIMEOUT 100 + +enum { + CMD_INPUT_0 = 0, + CMD_INPUT_1, + CMD_INPUT_2, + CMD_INPUT_3, + CMD_INPUT_4, + CMD_OUTPUT_0 = 8, + CMD_OUTPUT_1, + CMD_OUTPUT_2, + CMD_OUTPUT_3, + CMD_OUTPUT_4, + CMD_INVERSION_0 = 16, + CMD_INVERSION_1, + CMD_INVERSION_2, + CMD_INVERSION_3, + CMD_INVERSION_4, + CMD_CONFIG_0 = 24, + CMD_CONFIG_1, + CMD_CONFIG_2, + CMD_CONFIG_3, + CMD_CONFIG_4, +}; + +void pca9505_init(uint8_t slave_addr) { + static uint8_t s_init = 0; + if (!s_init) { + i2c_init(); + + s_init = 1; + } + + // TODO: could check device connected + // i2c_start(SLAVE_TO_ADDR(slave) | I2C_WRITE); + // i2c_stop(); +} + +bool pca9505_set_config(uint8_t slave_addr, pca9505_port_t port, uint8_t conf) { + uint8_t addr = SLAVE_TO_ADDR(slave_addr); + uint8_t cmd = 0; + switch (port) { + case 0: + cmd = CMD_CONFIG_0; + break; + case 1: + cmd = CMD_CONFIG_1; + break; + case 2: + cmd = CMD_CONFIG_2; + break; + case 3: + cmd = CMD_CONFIG_3; + break; + case 4: + cmd = CMD_CONFIG_4; + break; + } + + i2c_status_t ret = i2c_writeReg(addr, cmd, &conf, sizeof(conf), TIMEOUT); + if (ret != I2C_STATUS_SUCCESS) { + print("pca9505_set_config::FAILED\n"); + return false; + } + + return true; +} + +bool pca9505_set_polarity(uint8_t slave_addr, pca9505_port_t port, uint8_t conf) { + uint8_t addr = SLAVE_TO_ADDR(slave_addr); + uint8_t cmd = 0; + switch (port) { + case 0: + cmd = CMD_INVERSION_0; + break; + case 1: + cmd = CMD_INVERSION_1; + break; + case 2: + cmd = CMD_INVERSION_2; + break; + case 3: + cmd = CMD_INVERSION_3; + break; + case 4: + cmd = CMD_INVERSION_4; + break; + } + + i2c_status_t ret = i2c_writeReg(addr, cmd, &conf, sizeof(conf), TIMEOUT); + if (ret != I2C_STATUS_SUCCESS) { + print("pca9505_set_polarity::FAILED\n"); + return false; + } + + return true; +} + +bool pca9505_set_output(uint8_t slave_addr, pca9505_port_t port, uint8_t conf) { + uint8_t addr = SLAVE_TO_ADDR(slave_addr); + uint8_t cmd = 0; + switch (port) { + case 0: + cmd = CMD_OUTPUT_0; + break; + case 1: + cmd = CMD_OUTPUT_1; + break; + case 2: + cmd = CMD_OUTPUT_2; + break; + case 3: + cmd = CMD_OUTPUT_3; + break; + case 4: + cmd = CMD_OUTPUT_4; + break; + } + + i2c_status_t ret = i2c_writeReg(addr, cmd, &conf, sizeof(conf), TIMEOUT); + if (ret != I2C_STATUS_SUCCESS) { + print("pca9505_set_output::FAILED\n"); + return false; + } + + return true; +} + +bool pca9505_readPins(uint8_t slave_addr, pca9505_port_t port, uint8_t* out) { + uint8_t addr = SLAVE_TO_ADDR(slave_addr); + uint8_t cmd = 0; + switch (port) { + case 0: + cmd = CMD_INPUT_0; + break; + case 1: + cmd = CMD_INPUT_1; + break; + case 2: + cmd = CMD_INPUT_2; + break; + case 3: + cmd = CMD_INPUT_3; + break; + case 4: + cmd = CMD_INPUT_4; + break; + } + + i2c_status_t ret = i2c_readReg(addr, cmd, out, sizeof(uint8_t), TIMEOUT); + if (ret != I2C_STATUS_SUCCESS) { + print("pca9505_readPins::FAILED\n"); + return false; + } + + return true; +} diff --git a/drivers/gpio/pca9505.h b/drivers/gpio/pca9505.h new file mode 100644 index 0000000000..732ddb88ea --- /dev/null +++ b/drivers/gpio/pca9505.h @@ -0,0 +1,67 @@ +// Copyright 2022 nirim000 +// SPDX-License-Identifier: GPL-2.0-or-later + +#pragma once + +#include <stdint.h> +#include <stdbool.h> + +/** + * Port ID + */ +typedef enum { + PCA9505_PORT0, + PCA9505_PORT1, + PCA9505_PORT2, + PCA9505_PORT3, + PCA9505_PORT4, +} pca9505_port_t; + +/** + * Helpers for set_config + */ +enum { + ALL_NORMAL = 0, + ALL_INVERTED = 0xFF, +}; + +/** + * Helpers for set_config + */ +enum { + ALL_OUTPUT = 0, + ALL_INPUT = 0xFF, +}; + +/** + * Helpers for set_output + */ +enum { + ALL_LOW = 0, + ALL_HIGH = 0xFF, +}; + +/** + * Init expander and any other dependent drivers + */ +void pca9505_init(uint8_t slave_addr); + +/** + * Configure input/output to a given port + */ +bool pca9505_set_config(uint8_t slave_addr, pca9505_port_t port, uint8_t conf); + +/** + * Configure polarity to a given port + */ +bool pca9505_set_polarity(uint8_t slave_addr, pca9505_port_t port, uint8_t conf); + +/** + * Write high/low to a given port + */ +bool pca9505_set_output(uint8_t slave_addr, pca9505_port_t port, uint8_t conf); + +/** + * Read state of a given port + */ +bool pca9505_readPins(uint8_t slave_addr, pca9505_port_t port, uint8_t* ret); diff --git a/drivers/led/aw20216.c b/drivers/led/aw20216.c index 448accdcd3..55083936ef 100644 --- a/drivers/led/aw20216.c +++ b/drivers/led/aw20216.c @@ -53,6 +53,10 @@ # define AW_GLOBAL_CURRENT_MAX 150 #endif +#ifndef AW_SPI_MODE +# define AW_SPI_MODE 0 +#endif + #ifndef AW_SPI_DIVISOR # define AW_SPI_DIVISOR 4 #endif @@ -63,7 +67,7 @@ bool g_pwm_buffer_update_required[DRIVER_COUNT] = {false}; bool AW20216_write(pin_t cs_pin, uint8_t page, uint8_t reg, uint8_t* data, uint8_t len) { static uint8_t s_spi_transfer_buffer[2] = {0}; - if (!spi_start(cs_pin, false, 3, AW_SPI_DIVISOR)) { + if (!spi_start(cs_pin, false, AW_SPI_MODE, AW_SPI_DIVISOR)) { spi_stop(); return false; } diff --git a/drivers/led/issi/is31fl3733-simple.c b/drivers/led/issi/is31fl3733-simple.c index af006f756d..2f41a7b1a9 100644 --- a/drivers/led/issi/is31fl3733-simple.c +++ b/drivers/led/issi/is31fl3733-simple.c @@ -70,6 +70,10 @@ # define ISSI_CSPULLUP PUR_0R #endif +#ifndef ISSI_GLOBALCURRENT +# define ISSI_GLOBALCURRENT 0xFF +#endif + // Transfer buffer for TWITransmitData() uint8_t g_twi_transfer_buffer[20]; @@ -182,7 +186,7 @@ void IS31FL3733_init(uint8_t addr, uint8_t sync) { // Set de-ghost pull-down resistors (CSx) IS31FL3733_write_register(addr, ISSI_REG_CSPULLUP, ISSI_CSPULLUP); // Set global current to maximum. - IS31FL3733_write_register(addr, ISSI_REG_GLOBALCURRENT, 0xFF); + IS31FL3733_write_register(addr, ISSI_REG_GLOBALCURRENT, ISSI_GLOBALCURRENT); // Disable software shutdown. IS31FL3733_write_register(addr, ISSI_REG_CONFIGURATION, ((sync & 0b11) << 6) | ((ISSI_PWM_FREQUENCY & 0b111) << 3) | 0x01); diff --git a/drivers/led/issi/is31fl3733.c b/drivers/led/issi/is31fl3733.c index a2fdaa90fa..add998f256 100644 --- a/drivers/led/issi/is31fl3733.c +++ b/drivers/led/issi/is31fl3733.c @@ -69,6 +69,10 @@ # define ISSI_CSPULLUP PUR_0R #endif +#ifndef ISSI_GLOBALCURRENT +# define ISSI_GLOBALCURRENT 0xFF +#endif + // Transfer buffer for TWITransmitData() uint8_t g_twi_transfer_buffer[20]; @@ -172,7 +176,7 @@ void IS31FL3733_init(uint8_t addr, uint8_t sync) { // Set de-ghost pull-down resistors (CSx) IS31FL3733_write_register(addr, ISSI_REG_CSPULLUP, ISSI_CSPULLUP); // Set global current to maximum. - IS31FL3733_write_register(addr, ISSI_REG_GLOBALCURRENT, 0xFF); + IS31FL3733_write_register(addr, ISSI_REG_GLOBALCURRENT, ISSI_GLOBALCURRENT); // Disable software shutdown. IS31FL3733_write_register(addr, ISSI_REG_CONFIGURATION, ((sync & 0b11) << 6) | ((ISSI_PWM_FREQUENCY & 0b111) << 3) | 0x01); diff --git a/drivers/led/issi/is31fl3736.c b/drivers/led/issi/is31fl3736.c index 7752a3f6cb..e9943614d2 100644 --- a/drivers/led/issi/is31fl3736.c +++ b/drivers/led/issi/is31fl3736.c @@ -63,6 +63,10 @@ # define ISSI_CSPULLUP PUR_0R #endif +#ifndef ISSI_GLOBALCURRENT +# define ISSI_GLOBALCURRENT 0xFF +#endif + // Transfer buffer for TWITransmitData() uint8_t g_twi_transfer_buffer[20]; @@ -154,7 +158,7 @@ void IS31FL3736_init(uint8_t addr) { // Set de-ghost pull-down resistors (CSx) IS31FL3736_write_register(addr, ISSI_REG_CSPULLUP, ISSI_CSPULLUP); // Set global current to maximum. - IS31FL3736_write_register(addr, ISSI_REG_GLOBALCURRENT, 0xFF); + IS31FL3736_write_register(addr, ISSI_REG_GLOBALCURRENT, ISSI_GLOBALCURRENT); // Disable software shutdown. IS31FL3736_write_register(addr, ISSI_REG_CONFIGURATION, 0x01); diff --git a/drivers/led/issi/is31fl3737.c b/drivers/led/issi/is31fl3737.c index bce0c34b2c..932530ac0a 100644 --- a/drivers/led/issi/is31fl3737.c +++ b/drivers/led/issi/is31fl3737.c @@ -69,6 +69,10 @@ # define ISSI_CSPULLUP PUR_0R #endif +#ifndef ISSI_GLOBALCURRENT +# define ISSI_GLOBALCURRENT 0xFF +#endif + // Transfer buffer for TWITransmitData() uint8_t g_twi_transfer_buffer[20]; @@ -161,7 +165,7 @@ void IS31FL3737_init(uint8_t addr) { // Set de-ghost pull-down resistors (CSx) IS31FL3737_write_register(addr, ISSI_REG_CSPULLUP, ISSI_CSPULLUP); // Set global current to maximum. - IS31FL3737_write_register(addr, ISSI_REG_GLOBALCURRENT, 0xFF); + IS31FL3737_write_register(addr, ISSI_REG_GLOBALCURRENT, ISSI_GLOBALCURRENT); // Disable software shutdown. IS31FL3737_write_register(addr, ISSI_REG_CONFIGURATION, ((ISSI_PWM_FREQUENCY & 0b111) << 3) | 0x01); diff --git a/drivers/led/issi/is31fl3741.c b/drivers/led/issi/is31fl3741.c index 393b0179b5..ba6b6761a3 100644 --- a/drivers/led/issi/is31fl3741.c +++ b/drivers/led/issi/is31fl3741.c @@ -69,6 +69,10 @@ # define ISSI_CSPULLUP PUR_32KR #endif +#ifndef ISSI_GLOBALCURRENT +# define ISSI_GLOBALCURRENT 0xFF +#endif + #define ISSI_MAX_LEDS 351 // Transfer buffer for TWITransmitData() @@ -163,7 +167,7 @@ void IS31FL3741_init(uint8_t addr) { IS31FL3741_write_register(addr, ISSI_REG_CONFIGURATION, 0x01); // Set Golbal Current Control Register - IS31FL3741_write_register(addr, ISSI_REG_GLOBALCURRENT, 0xFF); + IS31FL3741_write_register(addr, ISSI_REG_GLOBALCURRENT, ISSI_GLOBALCURRENT); // Set Pull up & Down for SWx CSy IS31FL3741_write_register(addr, ISSI_REG_PULLDOWNUP, ((ISSI_CSPULLUP << 4) | ISSI_SWPULLUP)); diff --git a/drivers/painter/gc9a01/qp_gc9a01.c b/drivers/painter/gc9a01/qp_gc9a01.c index ad76d58b07..37700a28a4 100644 --- a/drivers/painter/gc9a01/qp_gc9a01.c +++ b/drivers/painter/gc9a01/qp_gc9a01.c @@ -102,12 +102,11 @@ const struct tft_panel_dc_reset_painter_driver_vtable_t gc9a01_driver_vtable = { .flush = qp_tft_panel_flush, .pixdata = qp_tft_panel_pixdata, .viewport = qp_tft_panel_viewport, - .palette_convert = qp_tft_panel_palette_convert, - .append_pixels = qp_tft_panel_append_pixels, + .palette_convert = qp_tft_panel_palette_convert_rgb565_swapped, + .append_pixels = qp_tft_panel_append_pixels_rgb565, }, - .rgb888_to_native16bit = qp_rgb888_to_rgb565_swapped, - .num_window_bytes = 2, - .swap_window_coords = false, + .num_window_bytes = 2, + .swap_window_coords = false, .opcodes = { .display_on = GC9A01_CMD_DISPLAY_ON, diff --git a/drivers/painter/ili9xxx/qp_ili9163.c b/drivers/painter/ili9xxx/qp_ili9163.c index beaac0fbb5..14363c7d04 100644 --- a/drivers/painter/ili9xxx/qp_ili9163.c +++ b/drivers/painter/ili9xxx/qp_ili9163.c @@ -67,12 +67,11 @@ const struct tft_panel_dc_reset_painter_driver_vtable_t ili9163_driver_vtable = .flush = qp_tft_panel_flush, .pixdata = qp_tft_panel_pixdata, .viewport = qp_tft_panel_viewport, - .palette_convert = qp_tft_panel_palette_convert, - .append_pixels = qp_tft_panel_append_pixels, + .palette_convert = qp_tft_panel_palette_convert_rgb565_swapped, + .append_pixels = qp_tft_panel_append_pixels_rgb565, }, - .rgb888_to_native16bit = qp_rgb888_to_rgb565_swapped, - .num_window_bytes = 2, - .swap_window_coords = false, + .num_window_bytes = 2, + .swap_window_coords = false, .opcodes = { .display_on = ILI9XXX_CMD_DISPLAY_ON, diff --git a/drivers/painter/ili9xxx/qp_ili9341.c b/drivers/painter/ili9xxx/qp_ili9341.c index 1f41dcfc0b..9608f109bd 100644 --- a/drivers/painter/ili9xxx/qp_ili9341.c +++ b/drivers/painter/ili9xxx/qp_ili9341.c @@ -74,12 +74,11 @@ const struct tft_panel_dc_reset_painter_driver_vtable_t ili9341_driver_vtable = .flush = qp_tft_panel_flush, .pixdata = qp_tft_panel_pixdata, .viewport = qp_tft_panel_viewport, - .palette_convert = qp_tft_panel_palette_convert, - .append_pixels = qp_tft_panel_append_pixels, + .palette_convert = qp_tft_panel_palette_convert_rgb565_swapped, + .append_pixels = qp_tft_panel_append_pixels_rgb565, }, - .rgb888_to_native16bit = qp_rgb888_to_rgb565_swapped, - .num_window_bytes = 2, - .swap_window_coords = false, + .num_window_bytes = 2, + .swap_window_coords = false, .opcodes = { .display_on = ILI9XXX_CMD_DISPLAY_ON, diff --git a/drivers/painter/ili9xxx/qp_ili9488.c b/drivers/painter/ili9xxx/qp_ili9488.c new file mode 100644 index 0000000000..55cf9f896f --- /dev/null +++ b/drivers/painter/ili9xxx/qp_ili9488.c @@ -0,0 +1,120 @@ +// Copyright 2021 Nick Brassel (@tzarc) +// SPDX-License-Identifier: GPL-2.0-or-later + +#include "qp_internal.h" +#include "qp_comms.h" +#include "qp_ili9488.h" +#include "qp_ili9xxx_opcodes.h" +#include "qp_tft_panel.h" + +#ifdef QUANTUM_PAINTER_ILI9488_SPI_ENABLE +# include <qp_comms_spi.h> +#endif // QUANTUM_PAINTER_ILI9488_SPI_ENABLE + +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// Common + +// Driver storage +tft_panel_dc_reset_painter_device_t ili9488_drivers[ILI9488_NUM_DEVICES] = {0}; + +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// Initialization + +bool qp_ili9488_init(painter_device_t device, painter_rotation_t rotation) { + // clang-format off + const uint8_t ili9488_init_sequence[] = { + // Command, Delay, N, Data[N] + ILI9XXX_CMD_RESET, 120, 0, + ILI9XXX_SET_PGAMMA, 0, 15, 0x00, 0x03, 0x09, 0x08, 0x16, 0x0A, 0x3F, 0x78, 0x4C, 0x09, 0x0A, 0x08, 0x16, 0x1A, 0x0F, + ILI9XXX_SET_NGAMMA, 0, 15, 0x00, 0x16, 0x19, 0x03, 0x0F, 0x05, 0x32, 0x45, 0x46, 0x04, 0x0E, 0x0D, 0x35, 0x37, 0x0F, + ILI9XXX_SET_POWER_CTL_1, 0, 2, 0x17, 0x15, + ILI9XXX_SET_POWER_CTL_2, 0, 1, 0x41, + ILI9XXX_SET_VCOM_CTL_1, 0, 3, 0x00, 0x12, 0x80, + ILI9XXX_SET_PIX_FMT, 0, 1, 0x66, + ILI9XXX_SET_RGB_IF_SIG_CTL, 0, 1, 0x80, + ILI9XXX_SET_FRAME_CTL_NORMAL, 0, 1, 0xA0, + ILI9XXX_SET_INVERSION_CTL, 0, 1, 0x02, + ILI9XXX_SET_FUNCTION_CTL, 0, 2, 0x02, 0x02, + ILI9XXX_SET_IMAGE_FUNCTION, 0, 1, 0x00, + ILI9XXX_SET_PUMP_RATIO_CTL, 0, 4, 0xA9, 0x51, 0x2C, 0x82, + ILI9XXX_CMD_SLEEP_OFF, 5, 0, + ILI9XXX_CMD_DISPLAY_ON, 20, 0 + }; + // clang-format on + qp_comms_bulk_command_sequence(device, ili9488_init_sequence, sizeof(ili9488_init_sequence)); + + // Configure the rotation (i.e. the ordering and direction of memory writes in GRAM) + const uint8_t madctl[] = { + [QP_ROTATION_0] = ILI9XXX_MADCTL_BGR | ILI9XXX_MADCTL_MY, + [QP_ROTATION_90] = ILI9XXX_MADCTL_BGR | ILI9XXX_MADCTL_MX | ILI9XXX_MADCTL_MV | ILI9XXX_MADCTL_MY, + [QP_ROTATION_180] = ILI9XXX_MADCTL_BGR | ILI9XXX_MADCTL_MX, + [QP_ROTATION_270] = ILI9XXX_MADCTL_BGR | ILI9XXX_MADCTL_MV, + }; + qp_comms_command_databyte(device, ILI9XXX_SET_MEM_ACS_CTL, madctl[rotation]); + + return true; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// Driver vtable + +const struct tft_panel_dc_reset_painter_driver_vtable_t ili9488_driver_vtable = { + .base = + { + .init = qp_ili9488_init, + .power = qp_tft_panel_power, + .clear = qp_tft_panel_clear, + .flush = qp_tft_panel_flush, + .pixdata = qp_tft_panel_pixdata, + .viewport = qp_tft_panel_viewport, + .palette_convert = qp_tft_panel_palette_convert_rgb888, + .append_pixels = qp_tft_panel_append_pixels_rgb888, + }, + .num_window_bytes = 2, + .swap_window_coords = false, + .opcodes = + { + .display_on = ILI9XXX_CMD_DISPLAY_ON, + .display_off = ILI9XXX_CMD_DISPLAY_OFF, + .set_column_address = ILI9XXX_SET_COL_ADDR, + .set_row_address = ILI9XXX_SET_PAGE_ADDR, + .enable_writes = ILI9XXX_SET_MEM, + }, +}; + +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// SPI + +#ifdef QUANTUM_PAINTER_ILI9488_SPI_ENABLE + +// Factory function for creating a handle to the ILI9488 device +painter_device_t qp_ili9488_make_spi_device(uint16_t panel_width, uint16_t panel_height, pin_t chip_select_pin, pin_t dc_pin, pin_t reset_pin, uint16_t spi_divisor, int spi_mode) { + for (uint32_t i = 0; i < ILI9488_NUM_DEVICES; ++i) { + tft_panel_dc_reset_painter_device_t *driver = &ili9488_drivers[i]; + if (!driver->base.driver_vtable) { + driver->base.driver_vtable = (const struct painter_driver_vtable_t *)&ili9488_driver_vtable; + driver->base.comms_vtable = (const struct painter_comms_vtable_t *)&spi_comms_with_dc_vtable; + driver->base.native_bits_per_pixel = 24; // RGB888 + driver->base.panel_width = panel_width; + driver->base.panel_height = panel_height; + driver->base.rotation = QP_ROTATION_0; + driver->base.offset_x = 0; + driver->base.offset_y = 0; + + // SPI and other pin configuration + driver->base.comms_config = &driver->spi_dc_reset_config; + driver->spi_dc_reset_config.spi_config.chip_select_pin = chip_select_pin; + driver->spi_dc_reset_config.spi_config.divisor = spi_divisor; + driver->spi_dc_reset_config.spi_config.lsb_first = false; + driver->spi_dc_reset_config.spi_config.mode = spi_mode; + driver->spi_dc_reset_config.dc_pin = dc_pin; + driver->spi_dc_reset_config.reset_pin = reset_pin; + return (painter_device_t)driver; + } + } + return NULL; +} + +#endif // QUANTUM_PAINTER_ILI9488_SPI_ENABLE + +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/drivers/painter/ili9xxx/qp_ili9488.h b/drivers/painter/ili9xxx/qp_ili9488.h new file mode 100644 index 0000000000..21b8f03322 --- /dev/null +++ b/drivers/painter/ili9xxx/qp_ili9488.h @@ -0,0 +1,37 @@ +// Copyright 2021 Nick Brassel (@tzarc) +// SPDX-License-Identifier: GPL-2.0-or-later + +#pragma once + +#include "gpio.h" +#include "qp_internal.h" + +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// Quantum Painter ILI9488 configurables (add to your keyboard's config.h) + +#ifndef ILI9488_NUM_DEVICES +/** + * @ |