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-rw-r--r--drivers/painter/comms/qp_comms_spi.c32
-rw-r--r--drivers/painter/comms/qp_comms_spi.h18
2 files changed, 26 insertions, 24 deletions
diff --git a/drivers/painter/comms/qp_comms_spi.c b/drivers/painter/comms/qp_comms_spi.c
index e644ba9f84..7534e844d8 100644
--- a/drivers/painter/comms/qp_comms_spi.c
+++ b/drivers/painter/comms/qp_comms_spi.c
@@ -10,8 +10,8 @@
// Base SPI support
bool qp_comms_spi_init(painter_device_t device) {
- struct painter_driver_t * driver = (struct painter_driver_t *)device;
- struct qp_comms_spi_config_t *comms_config = (struct qp_comms_spi_config_t *)driver->comms_config;
+ painter_driver_t * driver = (painter_driver_t *)device;
+ qp_comms_spi_config_t *comms_config = (qp_comms_spi_config_t *)driver->comms_config;
// Initialize the SPI peripheral
spi_init();
@@ -24,8 +24,8 @@ bool qp_comms_spi_init(painter_device_t device) {
}
bool qp_comms_spi_start(painter_device_t device) {
- struct painter_driver_t * driver = (struct painter_driver_t *)device;
- struct qp_comms_spi_config_t *comms_config = (struct qp_comms_spi_config_t *)driver->comms_config;
+ painter_driver_t * driver = (painter_driver_t *)device;
+ qp_comms_spi_config_t *comms_config = (qp_comms_spi_config_t *)driver->comms_config;
return spi_start(comms_config->chip_select_pin, comms_config->lsb_first, comms_config->mode, comms_config->divisor);
}
@@ -33,8 +33,10 @@ bool qp_comms_spi_start(painter_device_t device) {
uint32_t qp_comms_spi_send_data(painter_device_t device, const void *data, uint32_t byte_count) {
uint32_t bytes_remaining = byte_count;
const uint8_t *p = (const uint8_t *)data;
+ const uint32_t max_msg_length = 1024;
+
while (bytes_remaining > 0) {
- uint32_t bytes_this_loop = bytes_remaining < 1024 ? bytes_remaining : 1024;
+ uint32_t bytes_this_loop = QP_MIN(bytes_remaining, max_msg_length);
spi_transmit(p, bytes_this_loop);
p += bytes_this_loop;
bytes_remaining -= bytes_this_loop;
@@ -44,13 +46,13 @@ uint32_t qp_comms_spi_send_data(painter_device_t device, const void *data, uint3
}
void qp_comms_spi_stop(painter_device_t device) {
- struct painter_driver_t * driver = (struct painter_driver_t *)device;
- struct qp_comms_spi_config_t *comms_config = (struct qp_comms_spi_config_t *)driver->comms_config;
+ painter_driver_t * driver = (painter_driver_t *)device;
+ qp_comms_spi_config_t *comms_config = (qp_comms_spi_config_t *)driver->comms_config;
spi_stop();
writePinHigh(comms_config->chip_select_pin);
}
-const struct painter_comms_vtable_t spi_comms_vtable = {
+const painter_comms_vtable_t spi_comms_vtable = {
.comms_init = qp_comms_spi_init,
.comms_start = qp_comms_spi_start,
.comms_send = qp_comms_spi_send_data,
@@ -67,8 +69,8 @@ bool qp_comms_spi_dc_reset_init(painter_device_t device) {
return false;
}
- struct painter_driver_t * driver = (struct painter_driver_t *)device;
- struct qp_comms_spi_dc_reset_config_t *comms_config = (struct qp_comms_spi_dc_reset_config_t *)driver->comms_config;
+ painter_driver_t * driver = (painter_driver_t *)device;
+ qp_comms_spi_dc_reset_config_t *comms_config = (qp_comms_spi_dc_reset_config_t *)driver->comms_config;
// Set up D/C as output low, if specified
if (comms_config->dc_pin != NO_PIN) {
@@ -89,15 +91,15 @@ bool qp_comms_spi_dc_reset_init(painter_device_t device) {
}
uint32_t qp_comms_spi_dc_reset_send_data(painter_device_t device, const void *data, uint32_t byte_count) {
- struct painter_driver_t * driver = (struct painter_driver_t *)device;
- struct qp_comms_spi_dc_reset_config_t *comms_config = (struct qp_comms_spi_dc_reset_config_t *)driver->comms_config;
+ painter_driver_t * driver = (painter_driver_t *)device;
+ qp_comms_spi_dc_reset_config_t *comms_config = (qp_comms_spi_dc_reset_config_t *)driver->comms_config;
writePinHigh(comms_config->dc_pin);
return qp_comms_spi_send_data(device, data, byte_count);
}
void qp_comms_spi_dc_reset_send_command(painter_device_t device, uint8_t cmd) {
- struct painter_driver_t * driver = (struct painter_driver_t *)device;
- struct qp_comms_spi_dc_reset_config_t *comms_config = (struct qp_comms_spi_dc_reset_config_t *)driver->comms_config;
+ painter_driver_t * driver = (painter_driver_t *)device;
+ qp_comms_spi_dc_reset_config_t *comms_config = (qp_comms_spi_dc_reset_config_t *)driver->comms_config;
writePinLow(comms_config->dc_pin);
spi_write(cmd);
}
@@ -118,7 +120,7 @@ void qp_comms_spi_dc_reset_bulk_command_sequence(painter_device_t device, const
}
}
-const struct painter_comms_with_command_vtable_t spi_comms_with_dc_vtable = {
+const painter_comms_with_command_vtable_t spi_comms_with_dc_vtable = {
.base =
{
.comms_init = qp_comms_spi_dc_reset_init,
diff --git a/drivers/painter/comms/qp_comms_spi.h b/drivers/painter/comms/qp_comms_spi.h
index 9989987327..b3da86d573 100644
--- a/drivers/painter/comms/qp_comms_spi.h
+++ b/drivers/painter/comms/qp_comms_spi.h
@@ -13,36 +13,36 @@
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Base SPI support
-struct qp_comms_spi_config_t {
+typedef struct qp_comms_spi_config_t {
pin_t chip_select_pin;
uint16_t divisor;
bool lsb_first;
int8_t mode;
-};
+} qp_comms_spi_config_t;
bool qp_comms_spi_init(painter_device_t device);
bool qp_comms_spi_start(painter_device_t device);
uint32_t qp_comms_spi_send_data(painter_device_t device, const void* data, uint32_t byte_count);
void qp_comms_spi_stop(painter_device_t device);
-extern const struct painter_comms_vtable_t spi_comms_vtable;
+extern const painter_comms_vtable_t spi_comms_vtable;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// SPI with D/C and RST pins
# ifdef QUANTUM_PAINTER_SPI_DC_RESET_ENABLE
-struct qp_comms_spi_dc_reset_config_t {
- struct qp_comms_spi_config_t spi_config;
- pin_t dc_pin;
- pin_t reset_pin;
-};
+typedef struct qp_comms_spi_dc_reset_config_t {
+ qp_comms_spi_config_t spi_config;
+ pin_t dc_pin;
+ pin_t reset_pin;
+} qp_comms_spi_dc_reset_config_t;
void qp_comms_spi_dc_reset_send_command(painter_device_t device, uint8_t cmd);
uint32_t qp_comms_spi_dc_reset_send_data(painter_device_t device, const void* data, uint32_t byte_count);
void qp_comms_spi_dc_reset_bulk_command_sequence(painter_device_t device, const uint8_t* sequence, size_t sequence_len);
-extern const struct painter_comms_with_command_vtable_t spi_comms_with_dc_vtable;
+extern const painter_comms_with_command_vtable_t spi_comms_with_dc_vtable;
# endif // QUANTUM_PAINTER_SPI_DC_RESET_ENABLE
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-08 21:22:28 +0000